[lowrisc-dev] untethered rocket-chip simulation?

Gabriel L. Somlo gsomlo at gmail.com
Mon Jan 28 21:15:04 GMT 2019


On Mon, Jan 28, 2019 at 06:55:55PM +0000, Dr Jonathan Kimmitt wrote:
> I think your problem is that by default the Rocket net list is
> configured for 2-state simulation using Verilator, if you want
> to use 4-state simulation you need to configure the RANDOM_INIT...
> macros to do something sensible.

Oh, that's what all those RANDOMIZE_*_INIT `define options are for!

Turns out, using

  "-DRANDOMIZE_REG_INIT -DRANDOMIZE_MEM_INIT -DRANDOMIZE_DELAY=0.002"

did the trick! Further tinkering with the content of
rocket-chip/bootrom/bootrom.S does cause the simulation to read from
mem_[0_]ext in behav_srams.v, through all the layers of AXI interfaces
and everything!

Thanks for getting me unstuck (again :) !

--Gabriel

> It’s also possible and rather naff that a random init could put
> the CPU into an unknown state in which case, the solution is to
> try a different random seed. An alternative is to customise the
> FIRRTL writer so that something comes out which is more what an
> ASIC engineer would expect, ie everything zero that needs to be
> zero on reset input.

> > On 28 Jan 2019, at 17:32, Gabriel L. Somlo <gsomlo at gmail.com> wrote:
> > 
> > I'm trying to run the rocketchip through a simulator, but without
> > the (imho massive) tethering infrastructure that usually surrounds
> > it (gdb/fesvr/dtm/jtag), just to see how its bits and pieces wobble,
> > and to maybe see it tickle its AXI interface(s) to memory and MMIO.
> > 
> > So I grabbed the current rocket sources and built one of the
> > configurations (shouldn't much matter which one, but in my
> > case I picked DefaultFPGASmallConfig):
> > 
> >  git clone --recursive \
> >      https://github.com/freechipsproject/rocket-chip.git
> > 
> >  make RISCV=${HOME}/RISCV -C rocket-chip/vsim \
> >       verilog CONFIG=DefaultFPGASmallConfig
> > 
> > I wrote the smallest testbench wrapper I could think of, and also
> > replaced SimDTM (the default tether) with a stub returning 0s for
> > everything:
> > 
> >  // begin FILE: tb.v
> > 
> >  module testbench();
> > 
> >    // clock & reset:
> >    reg clk = 1'b1;
> >    always #5 clk = ~clk;
> >    reg rst = 1'b1;
> >    initial #103 rst = 1'b0;
> > 
> >    // DUT declaration:
> >    wire result;
> >    TestHarness dut (
> >        .clock(clk),
> >        .reset(rst),
> >        .io_success(result)
> >    );
> > 
> >    // DUT simulation:
> >    initial begin
> >        $dumpfile("testbench.vcd");
> >        $dumpvars(0, testbench);
> > 
> >        $monitor($time, " ########################################\n",
> >            "\t\tresult=%b\n", result,
> >            "\t\tpc=%h\n", dut.dut.tile.core.ex_reg_pc,
> >        );
> > 
> >        repeat (3) begin
> >            repeat (10) @(posedge clk);
> >            $display("+10 cycles");
> >        end
> >        $finish;
> >    end
> >  endmodule // testbench
> > 
> >  // stub "tether" to satisfy dependencies:
> >  module SimDTM(
> >    input clk,
> >    input reset,
> >    output        debug_req_valid,
> >    input         debug_req_ready,
> >    output [ 6:0] debug_req_bits_addr,
> >    output [ 1:0] debug_req_bits_op,
> >    output [31:0] debug_req_bits_data,
> >    input         debug_resp_valid,
> >    output        debug_resp_ready,
> >    input  [ 1:0] debug_resp_bits_resp,
> >    input  [31:0] debug_resp_bits_data,
> >    output [31:0] exit
> >  );
> >    assign debug_req_valid     =  1'b0;
> >    assign debug_resp_ready    =  1'b0;
> >    assign exit                = 32'h0;
> > 
> >    assign debug_req_bits_addr =  7'h0;
> >    assign debug_req_bits_op   =  2'h0;
> >    assign debug_req_bits_data = 32'h0;
> >  endmodule // SimDTM
> > 
> >  // end FILE: tb.v
> > 
> > I tried building this with both iverilog and VCS, so either:
> > 
> >  iverilog -s testbench -o tb.vvp tb.v \
> >    rocket-chip/src/main/resources/vsrc/AsyncResetReg.v \
> >    rocket-chip/src/main/resources/vsrc/EICG_wrapper.v \
> >    rocket-chip/src/main/resources/vsrc/plusarg_reader.v \
> >    rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultFPGASmallConfig.v \
> >    rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultFPGASmallConfig.behav_srams.v
> > 
> > or:
> > 
> >  vcs -q -nc -sverilog -top testbench -o tb.simv tb.v \
> >    rocket-chip/src/main/resources/vsrc/AsyncResetReg.v \
> >    rocket-chip/src/main/resources/vsrc/EICG_wrapper.v \
> >    rocket-chip/src/main/resources/vsrc/plusarg_reader.v \
> >    rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultFPGASmallConfig.v \
> >    rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultFPGASmallConfig.behav_srams.v
> > 
> > When I run the simulation (either via 'vvp -N tb.vvp' or the
> > VCS-produced './tb.simv'), I would expect the core to spin around
> > the "hang" loop at 0x10040 (as per the included bootrom), or to
> > start knocking about the "main memory" in behav_srams.v if I changed
> > the reset vector to 0x8000_0000. Instead, the simulated rocket-chip
> > is stuck in an undefined state:
> > 
> >    0 ########################################
> >    result=0
> >    pc=xxxxxxxxx
> > 
> >  +10 cycles
> >  C 0: 0 [0] pc=[0000000Xxxxxxxxx] W[r 0=xxxxxxxxxxxxxxxx][0] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: 1 [0] pc=[0000000Xxxxxxxxx] W[r 0=xxxxxxxxxxxxxxxx][0] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: 2 [0] pc=[0000000Xxxxxxxxx] W[r 0=xxxxxxxxxxxxxxxx][0] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: 3 [0] pc=[0000000Xxxxxxxxx] W[r 0=xxxxxxxxxxxxxxxx][0] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: 4 [x] pc=[0000000Xxxxxxxxx] W[r x=xxxxxxxxxxxxxxxx][x] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: X [x] pc=[0000000Xxxxxxxxx] W[r x=xxxxxxxxxxxxxxxx][x] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: X [x] pc=[0000000Xxxxxxxxx] W[r x=xxxxxxxxxxxxxxxx][x] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  C 0: X [x] pc=[0000000Xxxxxxxxx] W[r x=xxxxxxxxxxxxxxxx][x] R[r x=xxxxxxxxxxxxxxxx] R[r x=xxxxxxxxxxxxxxxx] inst=[xxxxxxxx] DASM(xxxxxxxx)
> >  ...
> > 
> > I'm sure I must be missing something (after all the rocket-chip
> > works just fine when hooked into the rest of lowRISC :).
> > 
> > I'm wondering if anyone on this list ever encountered something
> > similar, and what the missing piece of the puzzle might have been.
> > 
> > Thanks in advance for any clues,
> > --Gabriel
> > 
> 



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