[lowrisc-dev] FPGA utilization stats

Philipp Wagner lists at philipp-wagner.com
Mon Jan 7 17:37:12 GMT 2019

Hi Gabriel,

Am 07.01.19 um 17:19 schrieb Gabriel L. Somlo:
> After successfully building chip_top.bit in fpga/board/nexys4_ddr,
> how would one get a set of up-to-date FPGA resource utilization
> statistics, similar to what's shown at the bottom of
> https://www.lowrisc.org/docs/untether-v0.2/fpga-demo/ ?
> I tried digging through vivado.log, but none of the (many) numbers
> reported in there stuck out as immediately useful.
> Do I have to bring up the Vivado GUI and poke around with it, or
> is there a way to collect the info from vivado.log, or have I just
> missed it by not looking carefully enough?

Most statistics are not the vivado.log file, but in
DESIGNNAME.runs/*/*.rpt files, e.g.
DESIGNNAME.runs/impl_1/TOPLEVEL_utilization_placed.rpt for utilization
after the placement step, or
DESIGNNAME.runs/synth_1/TOPLEVEL_utilization_synth.rpt for utilization
reports after the synthesis.

Note that the only real utilization numbers are after place-and-route,
the post-synthesis numbers are an early guess and use "synthetic" units.

These files are generated by Vivado by default, you don't need to
execute additional TCL commands unless you need additional reports.


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