[lowrisc-dev] Simulation of lowRISC refresh-v0.6
Dr Jonathan Kimmitt
jrrk2 at cam.ac.uk
Mon Oct 29 09:20:22 GMT 2018
The main purpose of the refresh-v0.6 upgrade was to incorporate the
(almost) latest Rocket and make it much easier to upgrade the version of
Rocket in future. This new version of Rocket lacks
almost all of the customisations that were made by LowRISC (tag memory
and so on). This is the main reason for the re-think of the directory
structure. In order to get synthesis working again it was
also necessary to upgrade Vivado to the 2018.1 release. Unfortunately
even though the synthesis support is improved, there are issues with
simulation which I don't know how to solve just at the moment.
Part of the problem is that isim has lagged behind the synthesis engine
in support for O/S independence. Operation with vcs-mx using the
external simulator mode of Vivado is possible but we realise this
is prohibitively expensive outside academe or large companies. However
even if you have such a license there would appear to still be an issue
with compiling the encrypted Xilinx libraries under VCS. If
you use the GUI for this then there is a version conflict with shared
libraries (under Ubuntu 16.03 Xilinx's own shared library will be first
in LD_LIBRARY_PATH, which is too old for certain system utilities to run).
It may be if you use Xilinx's preferred O/S (Redhat Enterprise Linux 6),
which also supports vcs, then these problems will go away, however at
our lab this O/S is deprecated as too old and indeed the vital support
for Intel Skylake is uncertain).
This is all very unsatisfactory, but given that the FPGA emulator can be
up and running in less time than it takes to compile and launch a decent
size simulation, you can understand why we place much more
emphasis on emulation in our latest documentation. Of course developing
new blocks will require a simulator, but this is not such a problem
because in most cases the new RTL will be not Xilinx specific.
In terms of Verilator support the picture is clouded by the necessity to
make use of certain IP blocks which are VHDL only. Designing out these
problematical IP blocks would be the way forward,
but at the moment this is not the priority.
The other thing you noticed, that the memory map was no longer generated
in Chisel/Scala, is a good and a bad thing. For those who like Chisel
hacking, it was a positive thing, but there are quality issues with
having multiple generated Chisel netlists hanging around, and in
particular if the FPGA netlist is not the one that has passed ISA
simulation. Again this change was made to avoid major grief if Rocket
needed upgrading again, because it requires considerable rework of the
On 29/10/2018 02:38, Lucien Anti-Spam wrote:
> Hi devs,
> I was sort of bashing my way through the v0.5 for simulation when v0.6 came out. I thought it would be an easy move over; however it appears it maybe untested/broken?
> There seem to have been quite a bit of folder and tech movement. Here is what I noticed initially
> vcs/vsim folders:* Immediately I noticed the rule for "lowrisc_srcs" is wrong but can be fixed with $(MODEL) vs $(PROJECT),* then I noticed that the constants are no longer from scala but a hard-coded set (aww, scala way was quite sexy),* and then I noticed the verilog_srcs didnt match up any more, and I stopped here.
> Whats the general thoughts on simulation now?
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