[lowrisc-dev] lowrisc 0.5 release on custom Virtex 7 2000T

Anup Kini anupkini at gmail.com
Mon Jan 29 10:07:46 GMT 2018


Thanks a ton Jonathan.


Thanks & Regards,
Anup Kini.

On Mon, Jan 29, 2018 at 3:32 PM, Dr Jonathan Kimmitt <jrrk2 at cam.ac.uk>
wrote:

> The clocks (on NexysDDR) are:
>
> 100MHz - incoming crystal oscillator
>
> 200MHz - mig_sys_clk to DDR controller (divided down to 25MHz for
> processor clk output)
>
> 60MHz - clk_io_uart to UART (divided down to 12MHz for trace debugger
> interface)
>
> 120MHz - clk_pixel to VGA monitor
>
> 50MHz (clk_rmii, clk_rmii_quad quadrature clocks) to Ethernet RMII
>
> The mig_ui_clk is 50MHz corresponding to the 2:1 clock converter for AXI
> DDR memory.
>
> On a different board you may well be able to go faster but these are the
> settings that we know work on the Artix-7.
>
> Regards,
>
> Jonathan
>
> On 29/01/18 09:21, Anup Kini wrote:
>
> Hi All,
>
> I have gone through the code and need some clarification regarding the
> clocks so that I can configure the mig correctly.
>
> - riscv processor clock - 50 MHz - from mig additonal clock - Is this
> correct ?
> - mig - ui_clk - this returns 200 MHz, is this correct ?
> - uart16550 - is this clocked at 200 MHz or 50 MHz
>
> Looking forward for some help.
>
>
> Thanks & Regards,
> Anup Kini.
>
> On Tue, Jan 23, 2018 at 2:51 PM, Alex Bradbury <asb at lowrisc.org> wrote:
>
>> On 23 January 2018 at 09:17, Anup Kini <anupkini at gmail.com> wrote:
>> > Hi Jonathan,
>> >
>> > Thanks for pointing out the ethernet IP.
>> >
>> > Currently, I need to boot linux on a RISC-V based system and found
>> lowrisc
>> > to be simple and easy to follow.
>> > I can do without the ethernet IP for now, login through the UART
>> interface
>> > and work on building a open-emdedded layer for the filesystem.
>> > I did look at the v0.2, untethered version also, the main point being
>> easy
>> > to port to the Virtex 2000T boards that I have here.
>> >
>> > The end goal would be to integrate with REDEFINE, a massively parallel
>> many
>> > core architecture (this work was presented at the RISC V Workshop 2016.
>> Video
>> > @ 7:40 mins <https://www.youtube.com/watch?v=PCzAOYJa-xY>)
>>
>> Interesting, are there any published papers on REDEFINE?
>>
>> Best,
>>
>> Alex
>>
>
>
>


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