[lowrisc-dev] lowrisc 0.5 release on custom Virtex 7 2000T
anupkini at gmail.com
Mon Jan 29 09:21:59 GMT 2018
I have gone through the code and need some clarification regarding the
clocks so that I can configure the mig correctly.
- riscv processor clock - 50 MHz - from mig additonal clock - Is this
- mig - ui_clk - this returns 200 MHz, is this correct ?
- uart16550 - is this clocked at 200 MHz or 50 MHz
Looking forward for some help.
Thanks & Regards,
On Tue, Jan 23, 2018 at 2:51 PM, Alex Bradbury <asb at lowrisc.org> wrote:
> On 23 January 2018 at 09:17, Anup Kini <anupkini at gmail.com> wrote:
> > Hi Jonathan,
> > Thanks for pointing out the ethernet IP.
> > Currently, I need to boot linux on a RISC-V based system and found
> > to be simple and easy to follow.
> > I can do without the ethernet IP for now, login through the UART
> > and work on building a open-emdedded layer for the filesystem.
> > I did look at the v0.2, untethered version also, the main point being
> > to port to the Virtex 2000T boards that I have here.
> > The end goal would be to integrate with REDEFINE, a massively parallel
> > core architecture (this work was presented at the RISC V Workshop 2016.
> > @ 7:40 mins <https://www.youtube.com/watch?v=PCzAOYJa-xY>)
> Interesting, are there any published papers on REDEFINE?
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