[lowrisc-dev] additive (non-destructive) rebase to upstream rocket-chip

Dr Jonathan Kimmitt jrrk2 at cam.ac.uk
Sat Dec 1 07:33:54 GMT 2018


Dear Gabriel,

Here be dragons. You can find details of IR lengths and USER1-4 boundary 
scan command numbers here:

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

For the seven series as you know the IR length is 6 and the user chain 
numbers are 0x2, 0x3, 0x22, 0x23.

This information applies to all Artix-7 based FPGAs, regardless of what 
the board is. Kintex FPGAs are the same as well.

Regards,

Jonathan

On 01/12/2018 00:27, Gabriel L. Somlo wrote:
> Hi Jonathan,
>
> I took a quick detour to teach myself enough Scala and Chisel to
> be dangerous, and make the following attempt at rewriting lowRISC's
> changes to Rocket in an "additive", upstream-friendly way:
>
> https://github.com/gsomlo/rocket-chip/tree/gls-lowrisc-v02
>
> The names I picked might need a bit of help (xilinx vs. nexys4ddr,
> not sure the Xilinx JTAG numbers are the same across multiple
> Xilinx boards or specific to each one individually), and maybe my
> Chisel/Scala looks amateur (well, it *is* :), but with any luck
> some of this stuff might begin being palatable for pushing upstream,
> to lower the lowRISC maintenance burden (nothing would preclude
> freezing on a certain upstream commit, except they'd have to begin
> making their subsequent changes with our stuff in mind :)
>
> One small matching change would be needed against the nexys4_ddr
> submodule:
>
> ================================================
> diff --git a/Makefile b/Makefile
> index 82396ed..ded8140 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -22,7 +22,7 @@ example_dir = $(abspath ../../..)/fpga/bare_metal/examples
>   
>   project_name = lowrisc-chip-imp
>   BACKEND ?= v
> -CONFIG=DefaultConfig
> +CONFIG=LowRiscConfig
>   
>   VIVADO = vivado
>   
> @@ -88,8 +88,9 @@ lowrisc_headers = \
>   verilog_srcs = \
>   	$(top_dir)/src/main/verilog/chip_top.sv \
>   	$(top_dir)/src/main/verilog/spi_wrapper.sv \
> -	$(top_dir)/vsrc/AsyncResetReg.v \
> -	$(top_dir)/vsrc/plusarg_reader.v \
> +	$(base_dir)/src/main/resources/vsrc/AsyncResetReg.v \
> +	$(base_dir)/src/main/resources/vsrc/plusarg_reader.v \
> +	$(base_dir)/src/main/resources/vsrc/EICG_wrapper.v \
>   
>   verilog_headers = \
>   	$(top_dir)/src/main/verilog/config.vh \
> @@ -116,7 +117,7 @@ test_cxx_headers = \
>   #--------------------------------------------------------------------
>   
>   verilog: $(lowrisc_headers)
> -	make -C ../../../rocket-chip/vsim verilog
> +	make -C $(base_dir)/vsim verilog CONFIG=$(CONFIG)
>   
>   $(fpga_src):
>   
> diff --git a/script/make_project.tcl b/script/make_project.tcl
> index 95b569b..f7d99dc 100644
> --- a/script/make_project.tcl
> +++ b/script/make_project.tcl
> @@ -61,8 +61,9 @@ set files [list \
>                  [file normalize $base_dir/src/main/verilog/sd_cmd_serial_host.v] \
>                  [file normalize $base_dir/src/main/verilog/sd_data_serial_host.sv] \
>                  [file normalize $base_dir/src/main/verilog/nasti_channel.sv] \
> -               [file normalize $base_dir/vsrc/AsyncResetReg.v ] \
> -               [file normalize $base_dir/vsrc/plusarg_reader.v ] \
> +               [file normalize $base_dir/rocket-chip/src/main/resources/vsrc/AsyncResetReg.v ] \
> +               [file normalize $base_dir/rocket-chip/src/main/resources/vsrc/plusarg_reader.v ] \
> +               [file normalize $base_dir/rocket-chip/src/main/resources/vsrc/EICG_wrapper.v ] \
>                  [file normalize $base_dir/src/main/verilog/ascii_code.v] \
>                  [file normalize $base_dir/src/main/verilog/axis_gmii_rx.v] \
>                  [file normalize $base_dir/src/main/verilog/axis_gmii_tx.v] \
> ================================================
>
> Anyhow, please let me know what you think.
>
> Thanks,
> --Gabriel
>



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