[lowrisc-dev] Nexys debug communication [was: Multiple Rockets and Minions memory hierarchy]

Peter Stuge peter at stuge.se
Sat Jun 17 17:39:29 BST 2017


Hi again,

Dr Jonathan Kimmitt wrote:
> See below for clarification about reasons for not changing mode of 
> hardware communications if we can avoid it...
> 
> This my interpretation of the warning from Denis Steckelmacher
> 
> http://steckdenis.be/post-2016-06-25-fast-usb-connection-on-the-nexys-video-using-ft2232h.html
..
> It would appear that, once the synhronous FIFO is enabled, it can no 
> longer act as a Vivado compatible JTAG port.  However I have not tried it.

Thank you for this clarification!

I now understand the concern that if the FT2232H is used for debug
communication then Vivado would be blocked from using it for JTAG.

This is an important concern, but knowing FTDI chips and USB I don't
believe that these two uses are neccessarily mutually exclusive.

Denis looks at this quite far away from the FTDI chip, considering
only what happens when using the libftdi1 API, and narrowly,
considering only one of the many modes of FT2232H operation.

First, the FT2232H has two channels, A and B, exposed as two "USB
interfaces". A USB interface is a USB protocol term, generally not
directly exposed to users in operating systems, but indeed one USB
interface can and often does equate to one OS-specific interface for
users, such as /dev/ttyUSB0.

The two channels are mostly(!) independent, as evidenced by the two
/dev/ttyUSB* devices in Linux when both channels operate in the (most
common) "Async Serial UART" mode.

It is important to know how pins for the two channels are connected
on the board, because this determines how we can use the chip.

Digilent keeps the FT2232H section of the Nexys schematic secret.
That is unfortunate and annoying, since there is nothing deserving of
protection in that circuit. It will be quite simple. But at least the
Reference Manual tells us that JTAG and a data bus are connected to
the FPGA, with pin assignment for the data bus.

Digilent documents (in the RM) that the FT2232H can be used in both
async and sync FT245 modes.

There are 9 different channel modes in the FT2232H, and in many modes
the A and B channels are completely independent.


Denis looks at the very fastest mode, "FT245-style Synchronous FIFO",
in which the FT2232H provides a 60 MHz clock to the FPGA.

FTDI indeed very clearly states in their documentation that only channel A
can be used in this mode and that channel B is then not available.
("as all resources have been switched onto channel A")
This constraint is solely within the FT2232H.

So we know that channel A is used for the data bus, and channel B for JTAG.

If Vivado uses USB correctly then it only needs access to channel B, in
USB stack terminology "claiming the USB interface". Vivado should not
care if another process has claimed the channel A interface.

If so, then channel A can be used in a mode other than that Denis
looked at, e.g. FT245 async, to communicate with the FPGA, without
blocking JTAG.


FT245 async mode yields 10-12 MByte/s throughput so it's slower than
sync, but it is reliable, and having a single connection to the board
for both programming and debugging would be convenient. As would not
needing to buy a separate interface board. :)


The FPGA interface for async mode is:

FTDI asserts RXF# when PC->FTDI FIFO is not empty
FPGA asserts RD#
FPGA waits 15ns
FTDI is driving D[7..0]
FPGA waits 15ns
FPGA deasserts RD#
FTDI waits 1..14ns (then stops driving D[7..0])
FTDI deasserts RXF#
FTDI waits 49ns

FTDI asserts TXE# when FTDI->PC FIFO is not full
FPGA drives D[7..0]
FPGA waits 5ns
FPGA asserts WR#
FPGA waits 30ns (after 1..14ns, TXE# may be deasserted)
FPGA deasserts WR#
if (more_data && TXE# still asserted) then repeat; FPGA drives D[7..0]
if (not more_data) then FPGA drives SIWU low for 250ns
if (TXE# deasserted) then FPGA waits 49ns from TXE# deassert


I am happy to write software to make debug communication over channel A
work in parallell with Vivado JTAG if there is interest. I can't do the
FPGA side FT245-style async interface however, so someone would have to
help me with that part. It seems to me that we could finish it in a
single day if we worked together.


If the async mode throughput is insufficient, or if Vivado is clumsy
and falls over when someone else uses channel A, then the next best
option seems to be a FT600 FMC board connected to the Nexys.

Unlike previous FTDI products, the FT600 actually uses USB very well. 
FTDI drivers are irrelevant, we would just use our own software,
which I would also be happy to write. The required effort is low.

The UMFT600X and UMFT601X boards have a 16 or 32 bit wide FT245-like
sync channel with 66 MHz or 100 MHz clock and data on each clock cycle,
so throughput is significantly higher than with the FT2232H.


What are the requirements, or wishlist performance, for debug communication?


Regards

//Peter



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