Fwd: [lowrisc-dev] Multiple Rockets and Minions memory hierarchy
danielfollesoe at gmail.com
Thu Jun 1 00:28:32 BST 2017
Regarding the Nexys Video card I see two possibilities for an improved
debug link. The DPTI/ DSPI link (See section 7 of "https://reference.
I have run some basic loopback tests over DPTI at speed up to 5 MB/s using
the demo that comes with Digient ADEPT 2. Have also found a an AXI
component of DPTI Written in VHDL :"https://github.com/Digilent/
vivado-library/tree/master/ip/AXI_DPTI_1.0". Drivers for the FT2232H chip
is needed. FTDI makes their closed drivers "D2XX". An open alternative is
Here is a "proof of consept" that got me started:
In addition i have looked at Ethernet interface with the card. Have found
some resources on git specifically targets the Nexys Video Ethernet module.
These are described using VHDL, so might need some rewriting. I have some
experience working with VHDL and have done some translation from verilog to
VDHL av few years ago.
Just some thoughts on ways to get support for the much more capable Nexys
2017-05-30 19:14 GMT+02:00 Dr Jonathan Kimmitt <jrrk2 at cam.ac.uk>:
> The target board for the minion-v0.4 release is Nexys-4DDR. We had to cut
> out some optional features for this board. Unfortunately the next low cost
> board in the same series, the Nexys-Video, lacks flow control on its UART,
> which causes problems for the trace debugger. Our build system in principle
> supports SMP rocket systems that share L2-cache and DDR memory, coherence
> is managed by TileLink. I don't think anybody has built it for FPGA
> Jonathan Kimmitt
> LowRISC team member
> Sent from my iPhone
> > On 30 May 2017, at 17:33, Tobias Strauch <tobias at cloudx.cc> wrote:
> > Hi guys,
> > may I add a question to the one below:
> > 3) I know it has mentioned a few months ago, but what would be the
> target virtex eval board for the next lowrisc release. maybe Wei mentioned
> it (and the questions below) at the WS, but the sound is terrible.
> > thank you for your answer in adcance, see you in Hebden Bridge, cheers,
> >> Tobias Strauch <tobias at cloudx.cc> hat am 17. April 2017 um 12:39
> >> Hi Rob et al.,
> >> thank you for sharing an update on your wonderful project at the RISC-V
> WS in Munich.
> >> I’ve been following the lowRISC project closely and I was wondering, if
> I may ask you two questions.
> >> 1) Support for (many) MultiCores (except the Minions):
> >> Are you still planning to go for a solution, that supports multiple
> cores of the same kind (except the Minion Cores Network), so let’s say,
> multiple rockets, multiple BOOMs etc. I’m particular interested in how you
> solve the cache coherence\software\OS software problems that come with it.
> >> 2) Minions and local memory
> >> Will you attach local memory to the individual minions, and if so, how
> will your global memory hierarchy look like?
> >> Thank you so much in advance for your answers.
> >> Cheers, Tobias
> >> PS: Can’t wait to work with your next release.
> >> PPS: I think the survey on the RISC-V cores you mentioned is highly
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