[lowrisc-dev] Untethered lowRISC: run bbl using Verilator
ws327 at cam.ac.uk
Mon Jul 24 13:24:59 BST 2017
All of the verilog and C++ files listed are add-ons from lowRISC.
We use a SystemVerilog top-level while the rocket-chip from UCB is a
full Chisel design.
I am afraid these files cannot be directly applied on UCB's rocket-chip.
On 24/07/2017 12:35, Grady Chen wrote:
> Hi Wei,
> Thank you for your suggestion.
> I will try to use UCB Rocket-chip.
> But seems it doesn't have the following useful modules which make me
> easier to run it on velece2 simulator:
> grady at qt03:~/work/*lowrisc-chip*/src$ find . -name *.sv
> ./test/verilog/host_behav.sv <http://host_behav.sv>
> ./test/verilog/nasti_ram_behav.sv <http://nasti_ram_behav.sv>
> ./test/verilog/chip_top_tb.sv <http://chip_top_tb.sv>
> ./main/verilog/chip_top.sv <http://chip_top.sv>
> grady at qt03:~/work*/lowrisc-chip*/src$ find . -name "*.cpp"
> Are these modules still useful for UCB Rocket-chip?
> Grady Chen
> On Fri, Jul 21, 2017 at 12:24 AM, Wei Song <ws327 at cam.ac.uk
> <mailto:ws327 at cam.ac.uk>> wrote:
> I see. The BBL in pk is left there for Spike (the instruction set
> Depending on which board you are using (or does not matter for
> verilator), BBL can be found at fpga/board/<board>/bbl
> However, I must say, the BBL is really for FPGA demo, or Vivado
> simulation. I am not sure what would come up if it is simulated in
> I might have run Verilator simulation on it as well.
> If host interface is really what you want, I might suggest the
> Rocket-chip from UCB?
> So what is the specific reason for you to choose lowRISC?
> Anyway, tagged-memory-v0.1 does use a very old version of host
> interface. Note that it also needs different gcc compilers, one
> for newlib one for linux.
> And it runs only one a Zynq board (Zedboard). We do not support
> verilator simulation for that version either.
> On 20/07/2017 17:02, Grady Chen wrote:
>> Hi Wei,
>> The BBL, I got it from the following:
>> git clone -b untether-v0.2 --recursive
>> ls -l owrisc-chip/riscv-tools/riscv-pk/pk/bbl.c
>> Which BBL should I use if I would like to run it by Verilator?
>> I am using single core. Which version should I use if I would
>> like to use host interface? tagged-v0.1?
>> Grady Chen
>> On Thu, Jul 20, 2017 at 11:06 PM, Wei Song <ws327 at cam.ac.uk
>> <mailto:ws327 at cam.ac.uk>> wrote:
>> Hello Grady,
>> As I have mentioned, we were trying to remove the host
>> interface from the SoC in order to make it standalone. The
>> functions of the host interface is very much reduced.
>> This means there is no more host side and software should not
>> rely on the host side to fulfill I/O functions or any
>> functions really (except for exit simulation).
>> So where does this BBL come from? We do not support the
>> original BBL from UCB or SiFive. The BBL in lowRISC should
>> have been revised.
>> Is this host interface call is related to multicore and you
>> have configured to use multicore?
>> The 0.2v of lowRISC does not support multicore, I am afraid.
>> Thanks for the clarification,
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