[lowrisc-dev] Untethered lowRISC: run bbl using Verilator

Grady Chen gchen at viosoft.com
Wed Jul 12 08:27:13 BST 2017


Hi All,

For some reason, I am running bbl using Verilator.
The following are my steps:

grady at riscv:~/lowrisc-chip/riscv-tools/riscv-pk$ elf2hex 16 8192 build/bbl
> ../../vsim/bbl.hex

grady at riscv:~/lowrisc-chip/vsim$ ./DefaultConfig-sim-debug +vcd
+vcd_name=bbl.vcd +max-cycles=100000000 +load=bbl.hex | spike-dasm > bbl.log

Core 0 get unsolved tohost code 8cb0 *# This is what I expected.*

grady at riscv:~/untether/lowrisc-chip/vsim$ grep request bbl.log

memory read request: 1 @ 200

memory read request: 1 @ 240

memory read request: 1 @ 280

memory read request: 1 @ 2c80

memory read request: 1 @ be80

memory read request: 2 @ bfc0

memory read request: 1 @ 2cc0

memory read request: 1 @ 2d00

......


There is only the memory read request but no memory write request. Seems
not right.
Any one know how to make SD assembly instruction leads memory write
transaction?

--
Thanks,
Grady Chen


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