[lowrisc-dev] Interested in GSoC 2017

Yogesh Mahajan y.mahajan456 at gmail.com
Mon Feb 27 17:54:51 GMT 2017


Hello everyone,
First of all congratulation for getting selected in GSoC 2017. I'm Yogesh
from Mumbai and pursuing my Undergraduate degree in Electrical Engineering
at IIT Bombay. I am mostly interested in hardware design than software but
can work with software section too. I have overlooked the projects
proposals for GSoC 2017 and I would like to work on open-source IPs or
 CMSIS-DSP
library.
I am very comfortable with VHDL and have completed a number of small
projects as part of the curriculum as well as the hobby. Some of my recent
hardware projects are as follows:
1. Simple Multicycle RISC processor for FPGA (Complete and Tested)
2. 6 Stages Pipelined RISC processor for FPGA with UART
bootloader (Complete and Tested)
3. Superscalar RISC processor (Active)
4. Hardware abstraction layer to use ADC and DAC on FPGA/ CPLD (Complete ad
tested)
5. UART peripheral for FPGA/ CPLD (Complete and tested)
I have used Altera Cyclone IV FPGA/ MAX V CPLD for testing above projects.

So, how should I proceed for GSoC's application? Are there any extra topics
I need know before getting started?
Best regards,
Yogesh


More information about the lowrisc-dev mailing list