[lowrisc-dev] Re: Debug Taskgroup

kritik bhimani bhimanikritik at gmail.com
Wed Dec 27 06:05:52 GMT 2017

Thanks for your input Jonathan. I am currently looking into if glip can be
used as the debug transport module instead of JTAG in rocket-chip

On Tuesday, December 26, 2017, Dr Jonathan Kimmitt <jrrk2 at cam.ac.uk> wrote:

> Dear Kritik,
>   A usable debug capability is a high priority. The implementation of the
> RISCV debug specification on Rocket will need some adaptation since TAP IR
> lengths and available user codes on Xilinx are restricted, also the wiring
> of the JTAG signals on the simulation platform needs adapting to real
> hardware. We have not thought it worthwhile to generate any release notes
> for the new Rocket since a key part, the Linux port, is not yet working. It
> will take considerable effort to get the tag cache working again, but a
> student of Stefan is working on adapting the trace debugger as I understand
> it.
> Regards,
> Jonathan
> Sent from my iPhone
> > On 26 Dec 2017, at 06:24, kritik bhimani <bhimanikritik at gmail.com>
> wrote:
> >
> > Hi Alex/Stefan, I saw that you both are a part of the debug taskgroup. So
> > could you please let me know regarding any activity on Trace feature. I
> > wanted to know which features of the debug in previous revisions of
> lowRISC
> > should be ported to work with the latest rocket-chip. As features like
> > and System Control Module I don't think are needed any more. Instead I
> > think the aim should rather be to extend the existing debug
> infrastructure
> > in the latest rocket-chip to use features from open soc debug like glip,
> > CTM and STM and at the same time be compliant with the debug spec. This
> > will also help in future to integrate latest rocket-chip into lowRISC.
> > Secondly can an issue on the GitHub repo be raised stating all the
> features
> > that are yet to be ported from the previous revisions like trace debug,
> tag
> > cache and related infrastructure.

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