[lowrisc-dev] Re: [lowRISC/lowrisc-chip] Errors : Add a DMA master
device in LowRiSC (#66)
Dr Jonathan Kimmitt
jrrk2 at cam.ac.uk
Thu Aug 24 06:43:07 BST 2017
The port to a different FPGA is of moderate complexity depending on the
details of peripherals available.
The Kintex series primitives are slightly different to the Artix, which
is different again to Ultrascale,
and memory sizes and dynamic memory interfaces differ between boards.
Xilinx IP versions and supported Vivado versions need to change.
Sadly not every Vivado release is robust and software support is not
available to academic institutions.
You will need a different configuration of DDR controller in most cases,
it is unlikely the video and keyboard peripherals will be compatible,
which will mean a certain amount of rewriting. Also the XCF file also
has to be changed, because signal names and pins change with different
packages and boards.
UART to USB interfaces differ a lot between boards and while it is
relatively easy to emulate a PC interface at 115200 baud, it could be
difficult to get the trace interface working at an effective speed. For
this reason we have not included a port to the KC705 since moving to
Not every board has a SD-card interface, on some boards you may be able
to work with an external adapter.
Work has started on updating the KC705 support for debug-v0.3 on the
kc705_update branch and previous mention of VC707 support has been
discussed on this list. Also the Zedboard port was provided by a third
The Nexys4_video board was purchased of part of a plan to provide more
capacity, but turned out to be disappointing due to a lack of flow
control signals on the UART. Obviously hardware designers have
conflicting demands on them for different features when designing boards
and this results in them dropping features which they consider low
priority. Another issue is the lack of USB support in the FPGA on most
boards. USB endpoints tend to terminate in off-chip IP, whereas what we
would like is to implement the USB in the FPGA (subject to area
Looking ahead we would like to support Ethernet but there are many
different PHY chips on the different boards with multiple different
Another annoying problem is that multiple high-speed interfaces can
interfere with each other if used simultaneously, due to noise
considerations, bond wire inductance, and the generosity of decoupling
The decentralized nature of the git repositories makes it relatively
easy for a third party to contribute a board port.
On 24/08/17 02:45, jawadhy wrote:
> Thanks both for your answer. How difficult is it to port the
> lowRISCv0.4 to work with bigger FPGA? was it done by other team?
> You are receiving this because you commented.
> Reply to this email directly, view it on GitHub
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