[lowrisc-dev] KC705 support

Dr Jonathan Kimmitt jrrk2 at cam.ac.uk
Tue Aug 22 11:04:24 BST 2017


Dear List,

I have created kc705_update branch as a basis for supporting newer 
releases. Trace debugging is off by default because of the problems 
identified by Stefan. The obvious changes that have already been 
mentioned have been done. These need reviewing and testing. The build 
failure that was previously reported has been fixed, but the bitstream 
does not (yet) work on the FPGA board.

I am sharing this because there seemed to be a bit of interest. It would 
be a good learning exercise for a motivated engineer.

Regards,

Jonathan


On 22/08/17 09:32, Dr Jonathan Kimmitt wrote:
> Dear Armia,
>
> For users who would like a little more capacity it makes sense to 
> support a different board. Our build structure and Makefiles are 
> designed to make it easy to port to new boards. The vast majority of 
> the code will not need changing. The parts that do will be to do with 
> memory sizes and specific hardware support on the board that you choose.
>
> By comparison if you look at Xilinx example designs you will normally 
> find only a handful of boards are supported out of the box, if you 
> have a different board with different clock rates or peripherals, it 
> is not easy at first to figure out all the changes that might be needed.
>
> A second issue, as well as the pinout of the FPGA connecting to its 
> peripherals is the exact behaviour of the peripherals required to 
> implement a certain host function such as Trace Debugging. This was 
> the primary purpose of the upgrade from v0.2 to v0.3, and it relies on 
> some very specific behaviour of the USB to UART converter, which is 
> actually on the FPGA board. The higher layers of the trace interface 
> are hardware independent but specific hardware details take a lot of 
> debugging.
>
> Then there are Xilinx IP differences, such as DDR4 instead of DDR3. 
> This may be dealt with by using the v0.2 release as a template for the 
> new version. Also Xilinx boards tend to have annoying interfaces to 
> peripherals which are designed to demonstrate some special feature of 
> the FPGA, such as RocketIO, and are not suitable for general purpose 
> use. This is particularly true of the newer boards such as Ultrascale 
> and Ultrascale+.
>
> For all these reasons we have prioritised one particular board which 
> is low cost and has suitable peripherals for the majority of our user 
> base, which is academic. Those who have the budget to buy a high-end 
> board and development licenses may be assumed to have the resources to 
> make the port, which is in any case a useful learning exercise.
>
> Regards,
>
> Jonathan
>
>
> On 21/08/17 21:21, Armia Salib wrote:
>> Hello *,
>>
>> We bought KC705 board particularly to build a system that is based on 
>> LowRISC V0.3 project. We tried to execute "make bitstream" from 
>> "lowrisc-chip/fpga/board/kc705", but it gave the following errors:
>>
>> """
>> ERROR: [Synth 8-1031] dii_package is not declared 
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:3]
>> ERROR: [Synth 8-1766] cannot open include file consts.vh 
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:5]
>> ERROR: [Synth 8-1766] cannot open include file dev_map.vh 
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:6]
>> """"
>>
>> Is KC705 board supported for LowRISC V0.3 and V0.4? I can change 
>> "lowrisc-chip/fpga/board/kc705/Makefile" with the msissing files, 
>> however, I am not sure if I will face more surprises later. What are 
>> other changes you may expect to support KC705?
>>
>> Best regards,
>> Armia
>>
>
>




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