[lowrisc-dev] KC705 support

Sean Halle seanhalle at intensivate.com
Tue Aug 22 07:48:57 BST 2017

Thanks Wei,

   How much effort do you estimate will be required for the KC705 port?
For example, how many hours of developer time?

   Does it involve Chisel modifications?  Or is the effort only changes to
the build scripts?

   If we undertake this, we will be happy to contribute back :-)

   And if anyone else has made any progress, we would be happy to work



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On Mon, Aug 21, 2017 at 1:44 PM, Wei Song <wei.song at cl.cam.ac.uk> wrote:

> Hello Armia,
> KC705 is only officially supported for untether-v0.2.
> It is not supported for v0.3/0.4 only because the limited number of users
> and the limit time available on our end.
> There are numerous attempts to port lowRISC to KC705/VC707 board in recent
> years.
> I believe there must have been several successful ports, however, no one
> has contribute back yet.
> The port job is actually straight-forward. It is just not urgent enough
> for us to actually make it.
> Would you please file an issue on our GitHub? Therefore we can keep track
> it and may be have it done some time in the future.
> Even better, if you would like to port v0.3/0.4 to KC705 and contribut it
> back, we can definitely provide help and guide you for the whole process.
> To start the port for v0.3, the easier way I think is to modify the
> Makefile available for the Nexys4-DDR board into one supporting KC705.
> The major difference for these two boards is the memory controller.
> I cc.ed Jonathan who is now in charge of the minion/FPGA work for lowRISC.
> Best regards,
> Wei
> On 21/08/2017 21:21, Armia Salib wrote:
>> Hello *,
>> We bought KC705 board particularly to build a system that is based on
>> LowRISC V0.3 project. We tried to execute "make bitstream" from
>> "lowrisc-chip/fpga/board/kc705", but it gave the following errors:
>> """
>> ERROR: [Synth 8-1031] dii_package is not declared
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:3]
>> ERROR: [Synth 8-1766] cannot open include file consts.vh
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:5]
>> ERROR: [Synth 8-1766] cannot open include file dev_map.vh
>> [/home/armia/IntensivateRoot/lowrisc-chip/src/main/verilog/chip_top.sv:6]
>> """"
>> Is KC705 board supported for LowRISC V0.3 and V0.4? I can change
>> "lowrisc-chip/fpga/board/kc705/Makefile" with the msissing files,
>> however, I am not sure if I will face more surprises later. What are other
>> changes you may expect to support KC705?
>> Best regards,
>> Armia

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