[lowrisc-dev] GSoC16 : A virtual platform for lowRISC SoC ?

Guillaume Delbergue guillaume.delbergue at gmail.com
Sun Mar 13 00:32:05 GMT 2016


I’m a Ph.D student working on TLM standard and its application to non memory mapped interfaces, and mainly about protocols used in SoC. I’m interested in building a virtual platform for the lowRISC SoC based on the SystemC IEEE standard.
More and more project are developed using a top-down approach building first TLM LT models, then maybe AT,... until the RTL. Virtual platforms enable software developers to build drivers and test their code early using a virtual version. They bring software and hardware team to enable early software and early validation. As I can see, you’re talking in your "Plans for RISC-V in 2016 » presentation about SPI, I2C, I2S, UART IP, I think it would be interesting for the community to have a TLM LT level (for example) equivalent to ease hardware, driver development and testing.

What’s the interest of the community in such a project ? What about having an open source virtual platform based on the industry standard (IEEE 1666) ?

Let me know if you have any questions.


Guillaume Delbergue

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