[lowrisc-dev] MP-Rocketchip system communication
cillino.25 at gmail.com
Wed Mar 9 16:51:43 GMT 2016
we are trying to implement a generic Rocketchip multiprocessor system with
accelerators, interconnected by a NoC.
We are currently designing the system on the Zedboard and trying to understand
the communication between the ARM core and the Rocketchip through the frontend
server. We'd like to put two (or more) Rocketchips on the AXI bus with
different addresses and configure them to execute different programs using
separate DDR spaces.
The problem is that if, in Vivado, we change the Rocketchip memory address
space from 512MB to 256MB it doesn't work. Therefore we are analyzing frontend
server code to understand where the RISC-V executable is loaded (in the fesvr-
code, and exactly at which address). We found the LOAD_ELF macro inside
elfloader.cc, which calls memif->write, which in turn calls htif->
[read|write]_packet, which finally calls htif_zedboard->write: this last
function however seems to write always to the same AXI address, that is the
Rocketchip starting address on the AXI bus.
We then would appreciate any hint on the files or functions responsible of the
ELF load address and the starting address of the Rocketchip execution, in order
to be able to change that address for each different Rocketchip and make the
cores run in parallel executing different programs.
We are aware that the fesvr is capable to run only one Rocketchip at a time,
and solve its system calls, but we will consider that problem later on.
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