[lowrisc-dev] Re: Interested in GSoC opportunity [porting teaching
Alex.Bradbury at cl.cam.ac.uk
Tue Mar 8 09:46:39 GMT 2016
On 8 March 2016 at 08:00, Deepankar Tyagi
<deepankar.tyagi at st.niituniversity.in> wrote:
> I am a computer science student at undergrad level and would love to
> contribute to lowRISC development efforts by porting a teaching OS.
> I am currently in process of drafting proposal, this mail is an effort to
> seek guidance in order to define goals, scope and timeline of project.
Great, thanks for reaching out for clarification.
> Read the tutorials to figure out how to set up development and testing
> However somethings are not clear,
> On the ideas page the statement is "Porting one of these to RISC-V and to
> the lowRISC platform..."
> #1 Since lowRISC is RISC V based then will porting process be different for
> RISC V and lowRISC ?, also the toolchain in tutorial also mentions RISC V
lowRISC is a particular RISC-V implementation. Some aspects of a
RISC-V system (e.g. interrupt controller) aren't currently
standardised, so we may end up with a different solution to other
implementations. That said, for the moment we closely match the
reference Rocket implementation from Berkeley. For ease of
development, targeting QEMU or Spike is probably sensible.
> #2 Also I would be grateful if mentor(s) can give insight on what should be
> deliverable by GSoC midterm.
I think demonstrating that you have a clear understanding of the
amount of work involved and how to schedule your time over the course
of the summer is important for allowing us to evaluate your
application, so I'm wary of giving too much guidance here. Try to
understand exactly what steps would be required to complete the
project, then work out how long you think those will take. The advice
I would give is not to be over-ambitious.
> #3 Does the mentor(s) have any preference between xv6 and xinu ?
I prefer xv6 because the accompanying text and lecture material is
available at no cost.
> #4 I do not have a FPGA board and will be developing / testing on simulator,
> is that alright?
Yes that's fine. If the project goes in a direction where an FPGA
would be useful we can supply one.
> #5 Is there a preferred means to get/see the progress reports ?
That depends what you're most comfortable with. A weekly email to the
mentor is the minimum expected, though I think most students would
benefit from sending public updates to the mailing list (or posting to
a blog) in order to get wider feedback and advice.
Let me know if there are any other questions I can help with.
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