[lowrisc-dev] Problem compiling bare metal examples

Wei Song ws327 at cam.ac.uk
Thu Mar 3 15:23:25 GMT 2016


Great! Thanks for the feedback and the summary!

-Wei

On 03/03/2016 15:20, Alexis Ramos Amo wrote:
>
> Thank you for your support, I’ve solved the problem.
>
>  
>
> Running report_property [get_cells chip_top/ram_reg_1] {LOC} did the
> trick.
>
>  
>
> I’m going to summarize the solution for anyone in the same situation
>
>  
>
> 1.       At the “makefile” under “Verilog_srcs” I’ve added my own verilogs
>
> 2.       At “…/fpga/common/script” line number 17 I’ve changed
>
> Ø  /“ram_match = re.match(r”ram_reg_(\d+)”, line)”/
>
> With this
>
> Ø  /“ram_match = re.match(r”chip_top/ram_reg_(\d+)”, line)” /
>
> 3.       At “search_ramb.tcl” change
>
> Ø  /“foreach m [get_cells ram_reg_*] {put $m; report_property $m {LOC} }”/
>
> With this
>
> Ø  /“foreach m [get_cells chip_top/ram_reg_*] {put $m; report_property
> $m {LOC} }”/
>
> / /
>
> Inside Vivado my hierarchy is like this
>
> |
>
> |- my wrapper
>
> |--- verilog1
>
> |--- verilog2
>
> |--- chip_top
>
> |------- <chip_top default hierarchy>
>
> |- nasti_lite_bridge
>
>  
>
> Also because I want to write the bitstream on SPI Flash and a .bin
> file is needed instead of .bit one, I had to run the “write_cfgmem
> […]” command inside Vivado to convert from .bit to .bin after
> executing “make hello”.
>
>  
>
> I’ve used a Nexys4
>
>  
>
> Kind Regards
>
>  
>
>  
>
>  
>
> Alexis Ramos Amo
> Researcher / PhD Student
>
>  
>
> Electronic Design and Space Technology group Universidad Nebrija
>
>  
>
> La Dehesa de La Villa Campus
> 28040 Calle Pirineos, 55 – Madrid
>
> Spain
>
>
> (+34) 91 452 11 00 (ext. 2805)
>
> aramosam at nebrija.es <mailto:aramosam at nebrija.es>
>
> *
> *www.nebrija.com <http://www.nebrija.com/>
>
>  
>
> *De:*Wei Song [mailto:ws327 at cam.ac.uk]
> *Enviado el:* jueves, 03 de marzo de 2016 13:32
> *Para:* Alexis Ramos Amo; Stefan Wallentowitz;
> lowrisc-dev at lists.lowrisc.org
> *Asunto:* Re: [lowrisc-dev] Problem compiling bare metal examples
>
>  
>
> It might be an issue of name hierarchy?
> If you put chip_top into a submodule, get_cells may not find the ram
> as the name of rams now prefixed with module names.
> Can you double check whether there is any ram at all? And might be the
> name of rams are prefixed.
>
> -Wei
>
> On 03/03/2016 12:28, Alexis Ramos Amo wrote:
> > Thank you both for your answer,
>
> > 
>
> > I've uploaded the log to dropbox
>
> > https://www.dropbox.com/s/0mad2sylncu5qm9/search-ramb.log?dl=0
>
> > 
>
> > 
>
> > The modification I've made is integrating chip_top.sv (and all its hierarchy) inside
> the IP wrapper, alongside with the other verilogs. Of course I've
> declared I/O of chip_top into the IP wrapper and I've connected the
> clock given by the IP as output, to the chip_top clk
>
> > 
>
> > If I run report_property [get_cells ram_reg_1] {LOC} I get "No cells matched
> 'ram_reg_1'  . In the RTL module I see the same components as the
> default lowRISC configuration.
>
> > 
>
> > I'm going to try with don't touch constraints but any other ideas are welcome
>
> > Best regards
>
> > 
>
> > Alexis Ramos Amo 
>
> > 
>
> > -----Mensaje original-----
>
> > De: Wei Song [mailto:ws327 at cam.ac.uk]
>
> > Enviado el: jueves, 03 de marzo de 2016 12:29
>
> > Para: Stefan Wallentowitz; Alexis Ramos Amo;
> lowrisc-dev at lists.lowrisc.org <mailto:lowrisc-dev at lists.lowrisc.org>
>
> > Asunto: Re: [lowrisc-dev] Problem compiling bare metal examples
>
> > 
>
> > Hello Alexis and Stefan,
>
> > 
>
> > Strangely I cannot see the log attached but according to Stefan's confirmation, the
> problem indeed is related to the boot ram.
>
> > So the lowRISC SoC boots from an on-FPGA block-RAM named "ram" in chip_top.sv.
>
> > Search for comment "the inferred BRAM".
>
> > The script bmm_gen.py is trying to automatically identify this block-ram then
> the compiled hello executable can be loaded into it.
>
> > 
>
> > For your modification to the lowRISC SoC, have you changed anything related to
> this "ram", or is there any change to the chip-level interconnect that
> makes Vivado to optimize the ram away?
>
> > 
>
> > Best regards,
>
> > Wei
>
> > 
>
> > On 03/03/16 10:59, Stefan Wallentowitz wrote:
>
>     On 03.03.2016 11:53, Alexis Ramos Amo wrote:
>     >>> Hello Stefan, thank you for your answer.
>     >>>
>     >>> Here is the log.
>     >>>
>     >>> Best, Alexis
>     >>>
>     Hi Alexis,
>
>     from the log I can confirm it did not find the RAMs:
>
>     WARNING: [Vivado 12-180] No cells matched 'ram_reg_*'.
>
>     Maybe Wei has a good idea about this issue, otherwise I hope I can
>     find some time later today to have a look at my project logs to
>     compare them.
>
>     Best,
>     Stefan
>
> >> 
>
> >
>



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