[lowrisc-dev] Problem compiling bare metal examples

Wei Song ws327 at cam.ac.uk
Thu Mar 3 11:28:57 GMT 2016


Hello Alexis and Stefan,

Strangely I cannot see the log attached but according to Stefan's 
confirmation, the problem indeed is related to the boot ram.
So the lowRISC SoC boots from an on-FPGA block-RAM named "ram" in 
chip_top.sv.
Search for comment "the inferred BRAM".
The script bmm_gen.py is trying to automatically identify this block-ram 
then the compiled hello executable can be loaded into it.

For your modification to the lowRISC SoC, have you changed anything 
related to this "ram", or is there any change to the chip-level 
interconnect that makes Vivado to optimize the ram away?

Best regards,
Wei

On 03/03/16 10:59, Stefan Wallentowitz wrote:
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> On 03.03.2016 11:53, Alexis Ramos Amo wrote:
>> Hello Stefan, thank you for your answer.
>>
>> Here is the log.
>>
>> Best, Alexis
>>
> Hi Alexis,
>
> from the log I can confirm it did not find the RAMs:
>
> WARNING: [Vivado 12-180] No cells matched 'ram_reg_*'.
>
> Maybe Wei has a good idea about this issue, otherwise I hope I can
> find some time later today to have a look at my project logs to
> compare them.
>
> Best,
> Stefan
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