[lowrisc-dev] LowRISC SoC structure proposal v5

Reinoud Zandijk reinoud at NetBSD.org
Thu Jul 28 21:43:13 BST 2016


Hi Stefan,

thanks for reading my proposal. Its still draft of course!

On Sun, Jul 10, 2016 at 06:20:05PM +0200, Stefan Wallentowitz wrote:
> On 10.07.2016 12:59, Reinoud Zandijk wrote:
> > here my v5 proposal for review. Please do read and comment on it :)
> I read the proposal and try to associate it with what is going on for RISC-V
> run-control debugging. Did you consider Tim's debug ROM proposal as part of
> your proposal?

I didn't read Tims debug ROM proposal prior to this since the v5 of the
proposal started at the RISC-V conference at CERN. Reading it now, there is
some overlap but also some structural differences.

Both proposals allow a CPU to be externally investigated but Tims idea
significantly extends a core IMHO without allowing fast context switching.
Tims proposal even demands a (possibly shared?) piece of ROM placed in the
global address space and a piece of RAM per processor. Both could of course
only be visible when in debug mode of course but still, this has address space
issues. Running code on a halted CPU is asking for potential side effects even
though its in flat-memory in debug mode. I haven't found (yet) if it can take
exceptions and how it deals with it; is it just returning 0 then? As for JTAG
support, I'm not that into the spec, so I take that for granted :)

So in short, I think I agree more with Adreas Trabers critique in separating
the debugged core entirely and not adding yet-another mode. Adding that might
sprinkle quite some extra logic around where as some minor extra logic and MUX
around the register banks would suffice.

Corner cases in my design are cases like single step debugging or tracing a
userland program in an OS or the case when debugging with just one Application
CPU available need to be adressed but are not that complex, but could be
considered part of the hypervisor Minions exporting a debug device for the
domain.

> Unfortuantely, I have a few problems putting stuff together in my head.
> Do you by chance have some figures that can be used as reference?

I'll try to create some diagrams to clarify the various parts; if possible in
ASCII art :) but maybe a SVG might be more suited, we'll see.

Does this answer your questions a bit?

All the best,
Reinoud




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