[lowrisc-dev] Memory-mapped SPI flash on Nexys4?

Wei Song ws327 at cam.ac.uk
Thu Jul 28 14:54:03 BST 2016

Hello Michael,

It is possible to configure an FPGA using a bitstream in Flash. For this
purpose, there is no need to change any hardware design.
What I understand, the trick is all on the Vivado software.
As long as the bitstream is correctly put into the FLASH using Vivado,
with correct jumpers on board, FPGA will be configured from Flash.
See Nexys4DDR demos for more information.

I have not done this before and probably will not support it as a way to
run lowRISC demo, unless there are benefits to do so.

The changes I have made to current lowRISC is to allow reusing the spare
Flash space as an execution in place (XIP) ROM.
Therefore a bootloader, such as coreboot, can be put there.
Also with some benefit that the bootloader does not need to be
re-downloaded when hardware changed.

Next big release probably will be December or January next year with
tagged memory and minions.
Why not now?

Best regards,

On 28/07/2016 14:26, Michael Clark wrote:
> Hi Wei,
> Yes this is quite neat.
> I should try to pull your work and try it out.
> Does this mean we can persist the first stage and cold boot without downloading the bitstream when the device is power cycled? I tried this but my skills are not there at this level. I read something about the frequency of the Flash/EEPROM needing to be at a particular setting for it to load the bust ram from Flash/EEPROM.
> I would like to try the lowrisc-chip when you have another release...
> Thanks,
> Michael 
> Sent from my iPhone
>> On 21/07/2016, at 3:02 AM, ron minnich <rminnich at gmail.com> wrote:
>> The memory mapped SPI is great news! Thanks Wei!
>> ron
>> On Wed, Jul 20, 2016 at 7:58 AM Jonathan Neuschäfer <j.neuschaefer at gmx.net>
>> wrote:
>>>> On Wed, Jul 20, 2016 at 11:27:11AM +0100, Wei Song wrote:
>>>> Hello Jonathan,
>>>> Thanks for the explanation. It seems pretty clear why a memory mapped
>>>> flash is needed now.
>>>> The good news is, I just find out that modern SPI Flash chips do support
>>>> an XIP (execution in place) mode which is dedicated for this purpose and
>>>> the Xilinx Quad SPI IP already support the XIP mode.
>>> Good
>>>> So I think I can add support to this memory mapped flash to lowRISC
>>>> early next month, hopefully you still get time to try?
>>> Yes. The GSoC coding period ends mid-August, and I'll probably keep
>>> working on RISC-V/coreboot after the GSoC.
>>> Jonathan

More information about the lowrisc-dev mailing list