[lowrisc-dev] Memory-mapped SPI flash on Nexys4?

Michael Clark michaeljclark at mac.com
Thu Jul 28 14:26:50 BST 2016


Hi Wei,

Yes this is quite neat.

I should try to pull your work and try it out.

Does this mean we can persist the first stage and cold boot without downloading the bitstream when the device is power cycled? I tried this but my skills are not there at this level. I read something about the frequency of the Flash/EEPROM needing to be at a particular setting for it to load the bust ram from Flash/EEPROM.

I would like to try the lowrisc-chip when you have another release...

Thanks,
Michael 

Sent from my iPhone

> On 21/07/2016, at 3:02 AM, ron minnich <rminnich at gmail.com> wrote:
> 
> The memory mapped SPI is great news! Thanks Wei!
> 
> ron
> 
> On Wed, Jul 20, 2016 at 7:58 AM Jonathan Neuschäfer <j.neuschaefer at gmx.net>
> wrote:
> 
>>> On Wed, Jul 20, 2016 at 11:27:11AM +0100, Wei Song wrote:
>>> Hello Jonathan,
>>> 
>>> Thanks for the explanation. It seems pretty clear why a memory mapped
>>> flash is needed now.
>>> The good news is, I just find out that modern SPI Flash chips do support
>>> an XIP (execution in place) mode which is dedicated for this purpose and
>>> the Xilinx Quad SPI IP already support the XIP mode.
>> 
>> Good
>> 
>>> So I think I can add support to this memory mapped flash to lowRISC
>>> early next month, hopefully you still get time to try?
>> 
>> Yes. The GSoC coding period ends mid-August, and I'll probably keep
>> working on RISC-V/coreboot after the GSoC.
>> 
>> 
>> Jonathan
>> 



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