[lowrisc-dev] Memory-mapped SPI flash on Nexys4?
ws327 at cam.ac.uk
Thu Jul 28 12:52:29 BST 2016
I have added a memory mapped flash to lowrisc-chip, currently in branch
A very simple test program fpga/bare_metal/examples/flash.c is provided.
It just reads and prints the content of the flash to console.
Since the flash has a pre-built image from Digilient, I can see
something and it seems OK.
To run this test, go to fpga/board/nexys4_ddr
Then depending on which CONFIG is used in Makefile, you either need the
trace debugger to open a terminal or normal UART terminal.
It should constantly printing the flash content.
For more information about how to run it, see the tutorial for debug-v0.3 at
Is it possible that you can have try and tell me it is OK or something
else is needed or actually it has some bugs?
It can be buggy as I have just implemented an AXI bus narrower to make
On 20/07/2016 15:58, Jonathan Neuschäfer wrote:
> On Wed, Jul 20, 2016 at 11:27:11AM +0100, Wei Song wrote:
>> Hello Jonathan,
>> Thanks for the explanation. It seems pretty clear why a memory mapped
>> flash is needed now.
>> The good news is, I just find out that modern SPI Flash chips do support
>> an XIP (execution in place) mode which is dedicated for this purpose and
>> the Xilinx Quad SPI IP already support the XIP mode.
>> So I think I can add support to this memory mapped flash to lowRISC
>> early next month, hopefully you still get time to try?
> Yes. The GSoC coding period ends mid-August, and I'll probably keep
> working on RISC-V/coreboot after the GSoC.
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