[lowrisc-dev] ERROR: [Synth 8-439] module 'axi_quad_spi_0' not found [/home/rjones/d/lowrisc-chip/src/main/verilog/chip_top.sv:295]

Richard W.M. Jones rjones at redhat.com
Mon Jul 25 22:33:35 BST 2016


On Mon, Jul 25, 2016 at 09:44:55PM +0100, Wei Song wrote:
> Hello Rich,
> 
> It is recommended to use Vivado 2015.4 for the untethered version.
> I think it might because that the versions of the Xilinx IPs are
> out-of-dated when using Vivado 2016.2.
> Although for the axi_quad_spi itself, it actually should be OK.
> 
> I would suggest you to manually revise
> fpba/board/nexys4/script/make_project.tcl
> Remove all -version argument for create_ip commands.
> 
> Then
> 
> make cleanall
> make bitstream
> 
> Hopefully this can fix your issue.

OK.  Actually I had to remove one `-version' option already.
I'll remove them all and report back tomorrow.

> If not, I would check the log of make project and also use GUI to
> see why the IP is not generated.
> 
> I think it would be better to use debug-v0.3 though, as it is more
> updated and uses a simpler and cleaner structure.

Sure if this doesn't work I'll update to the 0.3 version.

Rich.

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