[lowrisc-dev] ERROR: [Synth 8-439] module 'axi_quad_spi_0' not found [/home/rjones/d/lowrisc-chip/src/main/verilog/chip_top.sv:295]

Wei Song ws327 at cam.ac.uk
Mon Jul 25 21:44:55 BST 2016


Hello Rich,

It is recommended to use Vivado 2015.4 for the untethered version.
I think it might because that the versions of the Xilinx IPs are 
out-of-dated when using Vivado 2016.2.
Although for the axi_quad_spi itself, it actually should be OK.

I would suggest you to manually revise 
fpba/board/nexys4/script/make_project.tcl
Remove all -version argument for create_ip commands.

Then

make cleanall
make bitstream

Hopefully this can fix your issue.

If not, I would check the log of make project and also use GUI to see 
why the IP is not generated.

I think it would be better to use debug-v0.3 though, as it is more 
updated and uses a simpler and cleaner structure.

Best regards,
Wei

On 25/07/16 19:25, Richard W.M. Jones wrote:
> Probably an elementary problem, but when compiling the FPGA
> demo ("make bitstream") for Nexys 4, I get:
>
> ERROR: [Synth 8-439] module 'axi_quad_spi_0' not found [/home/rjones/d/lowrisc-chip/src/main/verilog/chip_top.sv:295]
> ERROR: [Synth 8-285] failed synthesizing module 'chip_top' [/home/rjones/d/lowrisc-chip/src/main/verilog/chip_top.sv:6]
>
> axi_quad_spi is a piece of Xilinx IP?  I'm afraid this is where my
> knowledge of what's going on gets hazy.
>
> I'm using:
>
>   - Fedora 24 on x86_64 host
>   - Vivado v2016.2 (64 bit of course)
>   - untether-v0.2 (not for any particular reason, I could try 0.3)
>
> Everything else up to this point has worked pretty much fine.
>
> Rich.
>




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