[lowrisc-dev] PCR Interrupts

Alex Bradbury asb at asbradbury.org
Thu Jul 21 18:40:42 BST 2016


On 21 July 2016 at 18:32, Wei Song <ws327 at cam.ac.uk> wrote:
> Hello Francesco,
>
> The interrupt sources are simply or-reduced and connected to the irq pin of
> each core.
> There is an enable register (per core in PCR) which can be used to disable
> certain interrupt source.
> If a core decide to enable a source and response, it can read the pending
> register in pcr (if level triggered) or poll actual devices to find out the
> outstanding interrupts.
> If level-triggered, core needs to handle interrupt directly with the source
> device until the device withdraw its interrupt.
>
> I would say it is better to use a level triggered interrupt.
> Edge triggered interrupt may need special hardware treatment.
>
> We will add a proper interrupt controller in the next code release.

To clarify, this interrupt controller will be the PLIC described in
the 1.9 draft privileged spec
https://riscv.org/wp-content/uploads/2016/07/riscv-privileged-v1.9-1.pdf

The slides+video from Krste's talk at the 4th RISC-V Workshop last
week will hopefully go online soon, which outlines the principles
behind this interrupt controller. For now you'll have to make do with
the spec and my notes
(http://www.lowrisc.org/blog/2016/07/notes-from-the-fourth-risc-v-workshop/)
from the presentation. Krste describes the concept of an interrupt
"gateway" that abstracts away differences between edge vs level
triggered interrupts as they enter the PLIC. This is described in
section 7.4 of the 1.9 RISC-V privileged spec.

Best,

Alex



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