[lowrisc-dev] Memory-mapped SPI flash on Nexys4?
rminnich at gmail.com
Wed Jul 20 16:02:43 BST 2016
The memory mapped SPI is great news! Thanks Wei!
On Wed, Jul 20, 2016 at 7:58 AM Jonathan Neuschäfer <j.neuschaefer at gmx.net>
> On Wed, Jul 20, 2016 at 11:27:11AM +0100, Wei Song wrote:
> > Hello Jonathan,
> > Thanks for the explanation. It seems pretty clear why a memory mapped
> > flash is needed now.
> > The good news is, I just find out that modern SPI Flash chips do support
> > an XIP (execution in place) mode which is dedicated for this purpose and
> > the Xilinx Quad SPI IP already support the XIP mode.
> > So I think I can add support to this memory mapped flash to lowRISC
> > early next month, hopefully you still get time to try?
> Yes. The GSoC coding period ends mid-August, and I'll probably keep
> working on RISC-V/coreboot after the GSoC.
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