[lowrisc-dev] LowRISC SoC structure proposal v5
asb at asbradbury.org
Wed Jul 20 11:47:35 BST 2016
On 10 July 2016 at 11:59, Reinoud Zandijk <reinoud at netbsd.org> wrote:
> Hi folks,
> here my v5 proposal for review. Please do read and comment on it :)
Many thanks for sharing your design here. I wanted to summarise some
things that came to mind when reading it, and hopefully you can
correct me if I misunderstand
* In the second paragraph in detailed design, the requirement for a
debug bus is detailed. Presumably the argument is this is cheaper than
context switching previously described, and at least re-uses
infrastructure that would already be needed for debug?
* Do I understand correctly that the hypervisor minion would use
this in order to implement context switching between OSes on each CPU?
* Having a boot minion seems very sensible
* Since this message, the revised privileged spec draft 1.9 was
released. Do you have any thoughts on how this proposal might
integrate with the RISC-V PLIC design?
In general, as we're seeing in the device-tree vs config-string
discussion I think there's a tension between doing things cleanly vs
doing them in a way that matches existing devices and allows maximal
code reuse. That said, the work Greg KH did with Greybus+Unipro
suggests to me it should be possible to 'tunnel' existing devices if
I'll respond to your other thread with more thoughts about this, but I
think a key challenge is working out how to move forwards with a
proposal like this. Would you, for instance, be interested in
prototyping something along these lines in Spike or qemu?
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