[lowrisc-dev] Memory-mapped SPI flash on Nexys4?
ws327 at cam.ac.uk
Tue Jul 19 12:16:09 BST 2016
Sorry if I misunderstand something here.
Although SD card and Flash both use SPI interfaces, they are not
requested to use the same SPI interface.
To support Flash, a second Quad SPI interface can be added. Then there
should be no issue in using them at the same time.
As for choosing where the firmware and the Kernel is loaded from, they
can be loaded from flash as well if that is with benefits for some reason.
However, the future plan is to use CoreBoot, which I think providing
On 19/07/2016 03:34, Jonathan Neuschäfer wrote:
> Hello lowRISC developers,
> currently the SPI bus on the Nexys 4 DDR board is exposed through an
> explicit controller block, that software can talk (Q)SPI over.
> I think that lowRISC could do the following instead:
> - After reset, the SPI flash (whose primary purpose is to store a
> bitstream) is mapped into the physical address space. Reads from this
> area are translated to reads from the flash, writes are either
> discarded or cause a trap.
> - The existing SPI controller block is made available after a special
> control register is written, potentially only after the memory-mapped
> flash controller has been disabled. As I understand it, it would be
> risky to access the SPI bus through two different controllers more or
> less at the same time, because the commands and responses might mix
> - An alternate boot ROM could simply jump into the SPI flash, without
> performing any hardware initialization.
> The flash part on the Nexys 4 DDR is 16MiB big, of which about 4 are
> used for the bitstream, leaving plenty of space for boot firmware and,
> for example, a kernel and an initrd.
> Separating the boot firmware from the FPGA bitstream has the advantage
> that the bitstream doesn't need to be recompiled during boot firmware
> development, even if early initialization code is changed. A
> disadvantage of using the SPI flash is that it isn't as easily
> accessible as the µSD card slot. I also haven't tested whether Vivado
> can program the high 12MiB of the flash.
> What do you think about memory-mapping the flash?
> Best regards,
> Jonathan Neuschäfer
More information about the lowrisc-dev