[lowrisc-dev] Address bit width
ws327 at cam.ac.uk
Thu Jul 14 21:33:22 BST 2016
OK. No matter it is untether-v0.2 or the latest debug-v0.3, changing
PAddrBits to 39 bits should suppose to work.
The variable should also controls the AXI data width in chip_top.v at
least for the latest debug-v0.3.
There might be some complications because I have not tested it yet.
Please let me know it does not work somewhere.
On 14/07/2016 16:30, Francesco Viggiano wrote:
> Oh I'm sorry Wei, I meant the variable PAddrBits in Configs.scala . By
> the way I'm not using an up-to-date version of lowRISC.
> On Thu, Jul 14, 2016 at 1:19 PM Wei Song <ws327 at cam.ac.uk
> <mailto:ws327 at cam.ac.uk>> wrote:
> Hello Francesco,
> I did not find this pALen variable in current Configs.scala.
> However, even you managed to change this, it would not work.
> The current Rocket chip uses Sv39 address model by default, that means
> 39-bit physical address using 3-level page tables.
> I think it is much more possible to expand the physical address
> width to
> 39 and work out-straight.
> More than 39, it will need some significant changes.
> On 14/07/2016 13:06, Francesco Viggiano wrote:
> > Hello guys,
> > Do you support 64 bit addresses in order to have a total memory
> > larger then 4 Gb? I see there is "pALen" variable in
> Configs.scala, if I
> > change that value to 64 the compilation get broken. Do I need to
> set other
> > parameters to accomplish that purpose?
> > Bests,
> > Francesco
> | Francesco Viggiano, Columbia University, Staff associate researcher
> at Computer Science Building |
> | Phone: +1 646-9829-535, Skype ID: francesco.vgg |
> | Department of Computer Science 1214 Amsterdam Avenue |
> | Columbia University Mail Code 0401 | New York, NY 10027-7003 |
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