[lowrisc-dev] Re: [sw-dev] Is a de facto standard memory map
helpful or harmful?
krste at berkeley.edu
krste at berkeley.edu
Thu Jul 14 13:52:28 BST 2016
>>>>> On Wed, 13 Jul 2016 21:50:35 +0200, Arnd Bergmann <arnd at arndb.de> said:
| In previous information that I have seen about RISC-V, the idea
| was always to completely avoid MMIO and have discoverable hardware,
| which would nicely sidestep the problem entirely, but the information
| in the U5 Coreplex Series Manual gives up on that and just uses
| MMIO, presumably because otherwise you cannot easily reuse existing
| IP blocks. This means at least the Linux port will have to use
| a software device tree to describe what is actually there.
The fixed memory map is there for hardware implementers. Software
should always use the config string information to find where things
are on a platform.
| Unfortunately, the memory map described on page 12 of that document
| makes the same mistake as some ARM64 chips and makes the RAM
| location extremely sparse, with the first 14GB starting close to
| zero, but all RAM beyond that starting at 0x1_0000_0000_0000
| (256TB), which I guess requires using an extra level of page tables
| for the kind of linear mapping that Linux has. It's probably too
| late to change that, but I'd suggest that future implementations
| do it differently.
Platforms only need populate a single linear RAM address region. The
memory map describes the options where this could be put.
The reason we, and many others, adopt this style of layout is to
reduce hardware costs for smaller implementations which do not need to
provide all physical address bits and to support various DIMM sizes
without adding complexity/delay to memory accesses and coherence
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