[lowrisc-dev] Coding guidelines

Alex Bradbury asb at asbradbury.org
Mon Jul 11 20:24:00 BST 2016


On 11 July 2016 at 13:26, Gary Guo <xg244 at cam.ac.uk> wrote:
> Hi All,
>
> I wonder if there is already a coding guideline. I think it is necessary to have one to make sure contributed codes are of the same format. If we don't have one currently, I suggest that we can use or derive from existing ones, such as https://github.com/NetFPGA/netfpga/wiki/VerilogCodingGuidelines

If anyone knows of other good ones, please do share. I put the
question out to Twitter
https://twitter.com/lowRISC/status/752487522639437826. Andreas points
to Parallela's guidelines in the README of the 'oh' repo
https://github.com/parallella/oh.

At the lab, we've discussed before how it would be useful to document
the useful subset of SystemVerilog that seems to be reasonably well
supported by Verilator, Quartus, Vivado and the ASIC tools.

Best,

Alex



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