[lowrisc-dev] Questions about RISCV SOC implementation with AXI
david.fong at encoresemi.com
Fri Feb 19 17:52:18 GMT 2016
Thanks for making the lowRISC RISCV open source.
My company wants to use an open source SOC core to add specialized IP on AXI interface.
For Wei Song's RISCV implementation with AXI light interface (untethered to an ARM processor),
where to download it?
Secondly, is there a version of it that
replaces the FPGA peripherals with generic peripheral IP from opencores.org?
If not, how to replace the FPGA peripherals with something more generic.
Maybe there are other RISCV SOC implementations with AXI light interface
that has option to target to FPGA or to generic IP peripheral (just like the opencores.org or1200 SOC).
Any other ideas to find and download an untethered RISCV SOC with AXI interface and non-targeted FPGA peripheral IPs?
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