[lowrisc-dev] Re: Question on lowrisc project

Wei Song ws327 at cam.ac.uk
Tue Feb 23 15:40:50 GMT 2016


Hello Pawan,

Thanks Stefan for explaining the XIlinx IPs.

As for the coherence protocols used in the untethered release, it is set
to MESI in default, but it is configurable.
To change the configuration, you will need to modify case "L1ToL2",
TLCoherencePolicy in $TOP/src/main/scala/Configs.scala.

Best regards,
Wei

On 22/02/2016 05:23, Pawan Reddy Sibbala wrote:
> Hi Wei,
>
> I wanted to find out about the IP to see if we can modify the RTL of
> the memory controller. 
>
> On a different note, I was looking at the source code of the rocket
> system to see which coherence protocol was implemented in it, but I
> see that many coherence protocols are defined ( MSI , MESI , MOESI,
> directory based ) in the source files. I couldn't figure out which
> protocol is being used. Could you tell me what protocol is used for
> coherence? 
>
> Thanks and regards,
> Pawan
>
> On Sun, Feb 21, 2016 at 12:24 PM, Wei Song <ws327 at cam.ac.uk
> <mailto:ws327 at cam.ac.uk>> wrote:
>
>     Hello Pawan,
>
>     It is the one you get from the Vivado IP library (mig_7series ver
>     2.4).
>     I believe the memory controller is a soft one but the source is
>     encrypted.
>     To me, hard or soft does not make much difference.
>
>     Best regards,
>     Wei
>
>
>     On 21/02/2016 15:43, Pawan Reddy Sibbala wrote:
>>     Hello Wei, 
>>
>>     In your last mail, you mentioned that you're using Xilinx IPs for
>>     memory controller. Is it Xilinx Hard IP or are you using soft IP? 
>>
>>     Thanks and regards,
>>     Pawan
>>
>>     On Mon, Feb 15, 2016 at 11:26 AM, Pawan Reddy Sibbala
>>     <ps849 at cornell.edu <mailto:ps849 at cornell.edu>> wrote:
>>
>>         Thank you for the quick response, Wei. 
>>
>>         On Mon, Feb 15, 2016 at 11:02 AM, Wei Song <ws327 at cam.ac.uk
>>         <mailto:ws327 at cam.ac.uk>> wrote:
>>
>>             Hello Pawan,
>>
>>             On 15/02/2016 15:54, Pawan Reddy Sibbala wrote:
>>             > Hello Wei,
>>             >
>>             > I have two questions that I'd like to ask you.
>>             >
>>             > 1. The rocket core on the zedboard FPGA  currently runs
>>             at 25Hz. Could
>>             > you tell me the maximum frequency at which it can run ?
>>             I was
>>             > wondering if you already experimented with the
>>             parameters in
>>             > "clocking.vh" to find the maximum frequency.
>>
>>             No, I did not. The maximal frequency is in between of 25
>>             MHz and 50 MHz.
>>             For the same configuration and the same FPGA, running at
>>             50 MHz has some
>>             timing violations.
>>             The critical paths are in FPUs. So suppose if the FPU is
>>             disabled, it
>>             may run at 50 MHz.
>>             As running on FPGA is not the target and the design is
>>             not optimized for
>>             FPGA, there should be space for speed optimization.
>>             Even without any optimization, I believe it can easily
>>             run to 30 or 35
>>             MHz, which I had not tried.
>>
>>             >
>>             > 2. Does the new release of the untethered version of
>>             the rocketchip
>>             > use a opensource IP for implementing the Memory
>>             Controller or does it
>>             > use the Xilinx IP?
>>
>>             Those are Xilinx IPs.
>>
>>             >
>>             > Thanks and regards,
>>             > Pawan
>>             >
>>
>>             Best regards,
>>             Wei
>>
>>
>>
>>
>>         -- 
>>         Pawan Reddy Sibbala
>>         M.Eng ECE
>>         Cornell University
>>
>>
>>
>>
>>     -- 
>>     Pawan Reddy Sibbala
>>     M.Eng ECE
>>     Cornell University
>
>
>
>
> -- 
> Pawan Reddy Sibbala
> M.Eng ECE
> Cornell University



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