[lowrisc-dev] Re: Question on lowrisc project

Stefan Wallentowitz stefan at wallentowitz.de
Mon Feb 22 06:41:36 GMT 2016


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Hi Pawan,

On 22.02.2016 06:23, Pawan Reddy Sibbala wrote:
> Hi Wei,
> 
> I wanted to find out about the IP to see if we can modify the RTL
> of the memory controller.

Independent of whether it is a hard or soft IP, the RTL code is not
available for Xilinx targets. I was under the impression that in 7
Series FPGA the physical part is a hard macro, but it seems it all is
Soft-IP.

- From your questions I understand you are researching the memory
hierarchy? The question is if you can do what you want to do in the
user part of the memory controller, but I think most critical features
are closed source.

Best,
Stefan

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