[lowrisc-dev] Re: Question on lowrisc project

Wei Song ws327 at cam.ac.uk
Mon Feb 8 10:41:55 GMT 2016


Hello Pawan,

This is a legacy issue.
In short, No. The tagged memory release does not support L2$ although
the Config option is there.
It was found that with L2$ enabled, a coherence bug in L2$ will cause
issues in running SPEC, not mention booting a Linux.
Internally, I did fix the bug which allowed SPEC but failed to find the
problem with booting Linux.
For the following months Berkeley has gradually fixed bugs.
However, since the Rocket-chip has numerous updates that are not
directly compatible with the old release, there is no hope to make the
old release working withing with L2$.

The new untethered release has L2$ in default but currently without
tagged memory support.
We plan to re-integrated an expanded tag support later this year.

Best regards,
Wei

On 07/02/2016 06:27, Pawan Reddy Sibbala wrote:
> Hello Wei,
>
> I have a question about the memory hierarchy of the rocket chip
> configured on the zedboard FPGA.  Does the prebuilt FPGA image of the
> rocket chip for zedboard have an L2 $ cache configured? In the
> zedboard/src/verilog folder, I see that it DefaultFPGAConfig.v. From
> the "Configs.scala" file, I see that L2 $ is not included in the
> DefaultFPGAConfig setting. So, I think there is no L2$ configured in
> the prebuilt image. Am I correct?
>
> http://wsong83.github.io/publication/comparch/riscv2015.pdf
>
> But in the above paper, your configuration also has 128KB L2$. Did you
> use different configuration settings to include the L2 $? 
>
> Thanks and regards,
> Pawan  
>




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