Getting Focused was Fwd: [lowrisc-dev] Open GPU for the first CPU
asb at asbradbury.org
Tue Feb 17 14:51:54 GMT 2015
On 17 February 2015 at 10:32, ALadar-V <lowrisc-dev at aggregator.eu> wrote:
> Dne 17.2.2015 09:54, Alex Bradbury napsal(a):
>> We're very aware of the challenges and the timelines involved in
>> producing silicon. e.g. we have a 128-core research test chip on a
>> 40nm process taping out this summer. I'm not sure why you think we're
>> anywhere near running out of steam, on the contrary we're just getting
> Cool - what interfaces i.e. buses will it have for connecting external
> peripherals? The GPGPU thing might not be viable to do at the moment,
> but over time ... the development of it may be done (physically) by
> connecting some FPGA to a bus from lowrisc chip.
To be clear, this research chip is a different project to lowRISC (it
features simple cores using a custom instruction set architecture, if
we started it now they'd probably be RISC-V derived of course...).
Like many research chips, it doesn't feature a memory PHY+controller
and we use an FPGA as a Northbridge.
> Some relevant links
There are perhaps two obvious graphics-related projects that people
are likely to be interested in. The first, and more straight-forward
is a simple framebuffer with some 2D acceleration. The second is a
modern GPU that can be used for GPGPU applications and has high 3d
> One other possibility for the base of development of a GPU would be
> optimizing Mesa library to run in manymany threads, that could be
> spawned amongst those many cores of a lowrisc chip and render in
> software to some framebuffer. Will those lowrisc cores have all RV64G
> instruction set? And Hwacha accelerators?
You may find llvmpipe of interest http://www.mesa3d.org/llvmpipe.html
We haven't yet evaluated exactly what instruction set extensions the
minion cores will support. I would expect RV32I/RV64I with some
targeted extensions for use in IO processing tasks.
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