[lowrisc-dev] Codename for architecture (GNU autotools, etc)?
asb at asbradbury.org
Sat Nov 1 17:33:12 GMT 2014
On 1 November 2014 15:01, Manuel A. Fernandez Montecelo
<manuel.montezelo at gmail.com> wrote:
> According to the website, the processor used will be RISC-V 64 bits. I
> could not find any mentions about the endianness or other details that I
> am interested in. Follows a preamble, doubts at bottom.
It's relatively early days for the project. We're just now getting
people working full-time on it, so expect many more details in the not
too distant future. Answers inline below.
> In recent times and for the most popular devices, ARM seems to go mostly
> with little endian, but there are also big-endian systems. IBM created
> and seems to be investing more effort in ppc64el after having ppc64,
> because apparently there is a stronger demand for customers. MIPS have
> also mips/mipsel and mips64/mips64el. In these cases (and same for many
> other CPUs), they have "registered" the full range of architecture names
> in these GNU autotools files, while there is only the aforementioned
> "riscv32 | riscv64" for RISC-V, with no "le/el" or "be/eb" attached.
Little endian is our priority, I don't see any real benefit in
splitting effort and I doubt there's enough interest in big-endian.
There's nothing stopping a big-endian RISC-V implementation, but is
there really demand for it?
> So, my doubts are:
> - RISC-V is little-endian in principle, so I guess that the names above
> "riscv32 | riscv64" will imply little-endianness, but the ISA manual
> says that there can be big or bi-endian variants.
> Which one does lowRISC plan to use? And what will be the codename of
> the architecture in that case -- "riscv64el/-le", "riscv64eb/-be", or
> just plainly "riscv64" (implying little endian)?
I suppose these are issues to be sorted out with the wider risc-v
community. The main processor core will be RV64 'G' as described in
the ISA spec (i.e. base integer spec + mul/div + atomics + float +
double) which is what I imagine riscv32/risc64 would commonly be
interpreted as. For compilers, we'll want something like
march/mcpu/mtune to specify compilation for a specific implementation
with given extensions.
> - Does lowRISC plan to use different extensions or modifications of
> RISC-V, so that the architecture name will be different from
> "riscv64*" in any case?
We will have instruction set extensions for manipulating our tagged
memory support (initial thoughts on tagged memory are here
https://speakerdeck.com/asb/lowrisc-a-first-look). For arm, you can
specify -march=armv8-a+crc to indicate armv8-a with the optional crc
extensions. Possibly we'd have something similar. I can't answer
precisely, because this needs a bigger conversation with the wider
RISC-V community, and the GCC and LLVM community who can advise on how
well the architecture feature selection interface works on existing
> - What would be the architecture triplet name, for GNU toolchain? The
> compiler from RISC-V github repositories so far provides:
Same as above really.
> Maybe some of these questions are not decided yet, or things like naming
> in GNU autotools files depend mostly on decisions to be taken by RISC-V
> folks rather than people involved in list... But I would be grateful of
> any information and pointers that you can provide.
Sorry this response doesn't contain many solid answers, as you say a
lot of this comes down to the RISC-V, GCC, and LLVM communities.
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