[lowrisc-dev] lowRISC SoC structure / communication between application cores and minions

Alex Bradbury asb at asbradbury.org
Mon Dec 22 16:27:23 GMT 2014


On 19 December 2014 at 14:55, Reinoud Zandijk <reinoud at netbsd.org> wrote:
> Dear folks,
>
> i'd like to propose a novel way of structuring the SoC. I'll first try to put
> it into an ASCII art :)

Hi Reinoud, many thanks for writing up your thoughts on this, and for
all your contributions/ideas to date.


> (*) Each minion has a separate two way FIFO communication channel to the
> Application CPUs. Its the Hypervisors task to prevent simultanious access.

One FIFO shared between multiple applications CPUs? Having to trap the
the hypervisor for any send on the FIFO seems unfortunate. An
individual guest VM or even user process with appropriate permissions
having the ability to send directly would seem ideal, even if it does
make the network slightly more complex.

As the FIFO is shown separately to the memory-based DMA requests my
understanding is you are proposing app->minion communication is done
via registers.

> (**) DMA channel for each minion, programmable only by the Minion side since
> Application CPUs don't know where memory is in the Minion nor know if its
> space is free.

I like this.

> The `Minions' don't have tagged memory and are not tag aware and will write
> all tags as the default and/or insecure data; this to ensure that no tricks
> can be played with it. They also don't need to have virtual memory support nor
> be coherent with anything.

Minions not supporting tagged memory doesn't seem to be a necessary
consequence of this (though given the lack of coherency, it may be
easier to reason about to just disable it).

Alex



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