[lowrisc-dev] Tag system implementation questions

hga at ancell-ent.com hga at ancell-ent.com
Wed Dec 17 19:38:12 GMT 2014

Note that I am a ... dilettante in this area.  I've never worked at this
level, but got very interested in tagged architectures from exposure in
the very early '80s to Lisp Machines, which used 8 bit tags for things
like dynamic typing.

That said, in trying to figure out how the lowRISC tagging system per
memo 2014-01 might work and perform, I wonder:

Where will the backing store of the tag cache come from?

If not from stealing bits from 72 bit wide ECC DIMMs (which I don't
get the impression is the plan, although I wonder if ECC/parity will
be supported), how will dirty tags be written if tag cache lines
aren't 64 bits?

Related, what sort of tag cache organizations are you looking at?  E.g.
how can the mooted "can be small" 8KiB tag cache most take advantage of
its 32KiB possible entries?

- Harold

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