netsurf-commits April 2019

netsurf-commits@netsurf-browser.org

1 participants
4 discussions

netsurf: branch master updated. release/3.8-111-gccb499b

by NetSurf Browser Project

Gitweb links: ...log http://git.netsurf-browser.org/netsurf.git/shortlog/ccb499b80057a8241829a... ...commit http://git.netsurf-browser.org/netsurf.git/commit/ccb499b80057a8241829a3b... ...tree http://git.netsurf-browser.org/netsurf.git/tree/ccb499b80057a8241829a3ba1... The branch, master has been updated via ccb499b80057a8241829a3ba11e5f87013739c8d (commit) from 1a170f9f322416e14b0b11b999b61efa6bcdf8fe (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=ccb499b80057a824182... commit ccb499b80057a8241829a3ba11e5f87013739c8d Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Release guigfx drawhandle diff --git a/frontends/amiga/bitmap.c b/frontends/amiga/bitmap.c index 0fde677..32b9b12 100644 --- a/frontends/amiga/bitmap.c +++ b/frontends/amiga/bitmap.c @@ -531,17 +531,18 @@ static inline struct BitMap *ami_bitmap_get_generic(struct bitmap *bitmap, } ami_bitmap_rgba_to_argb(bitmap); - bitmap->drawhandle = ObtainDrawHandle(NULL, + if(bitmap->drawhandle = ObtainDrawHandle(NULL, &rp, scrn->ViewPort.ColorMap, GGFX_DitherMode, dithermode, - TAG_DONE); - - APTR ddh = CreateDirectDrawHandle(bitmap->drawhandle, - bitmap->width, bitmap->height, - width, height, NULL); - - DirectDrawTrueColor(ddh, (ULONG *)amiga_bitmap_get_buffer(bitmap), 0, 0, TAG_DONE); - DeleteDirectDrawHandle(ddh); + TAG_DONE)) { + APTR ddh = CreateDirectDrawHandle(bitmap->drawhandle, + bitmap->width, bitmap->height, + width, height, NULL); + + DirectDrawTrueColor(ddh, (ULONG *)amiga_bitmap_get_buffer(bitmap), 0, 0, TAG_DONE); + DeleteDirectDrawHandle(ddh); + ReleaseDrawHandle(bitmap->drawhandle); + } ami_bitmap_argb_to_rgba(bitmap); } else { if(guigfx_warned == false) { ----------------------------------------------------------------------- Summary of changes: frontends/amiga/bitmap.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/frontends/amiga/bitmap.c b/frontends/amiga/bitmap.c index 0fde677..32b9b12 100644 --- a/frontends/amiga/bitmap.c +++ b/frontends/amiga/bitmap.c @@ -531,17 +531,18 @@ static inline struct BitMap *ami_bitmap_get_generic(struct bitmap *bitmap, } ami_bitmap_rgba_to_argb(bitmap); - bitmap->drawhandle = ObtainDrawHandle(NULL, + if(bitmap->drawhandle = ObtainDrawHandle(NULL, &rp, scrn->ViewPort.ColorMap, GGFX_DitherMode, dithermode, - TAG_DONE); - - APTR ddh = CreateDirectDrawHandle(bitmap->drawhandle, - bitmap->width, bitmap->height, - width, height, NULL); - - DirectDrawTrueColor(ddh, (ULONG *)amiga_bitmap_get_buffer(bitmap), 0, 0, TAG_DONE); - DeleteDirectDrawHandle(ddh); + TAG_DONE)) { + APTR ddh = CreateDirectDrawHandle(bitmap->drawhandle, + bitmap->width, bitmap->height, + width, height, NULL); + + DirectDrawTrueColor(ddh, (ULONG *)amiga_bitmap_get_buffer(bitmap), 0, 0, TAG_DONE); + DeleteDirectDrawHandle(ddh); + ReleaseDrawHandle(bitmap->drawhandle); + } ami_bitmap_argb_to_rgba(bitmap); } else { if(guigfx_warned == false) { -- NetSurf Browser

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netsurf: branch master updated. release/3.8-110-g1a170f9

by NetSurf Browser Project

Gitweb links: ...log http://git.netsurf-browser.org/netsurf.git/shortlog/1a170f9f322416e14b0b1... ...commit http://git.netsurf-browser.org/netsurf.git/commit/1a170f9f322416e14b0b11b... ...tree http://git.netsurf-browser.org/netsurf.git/tree/1a170f9f322416e14b0b11b99... The branch, master has been updated via 1a170f9f322416e14b0b11b999b61efa6bcdf8fe (commit) via ac46ecbc1c2e756af6c2decfbd5e0a9d332fa781 (commit) from 35dbf07440cb6c5c26e1dbe2f7cd83ad95b745e1 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=1a170f9f322416e14b0... commit 1a170f9f322416e14b0b11b999b61efa6bcdf8fe Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Re-instate accidental removal of pkg-config for curl/openssl diff --git a/frontends/amiga/Makefile b/frontends/amiga/Makefile index b71ae3c..421be0e 100644 --- a/frontends/amiga/Makefile +++ b/frontends/amiga/Makefile @@ -17,16 +17,18 @@ $(eval $(call feature_enabled,AMISSL,-DWITH_AMISSL -D__NO_NET_API -D__NO_NETINCL CFLAGS += -I$(GCCSDK_INSTALL_ENV)/include CFLAGS += $(shell $(PKG_CONFIG) --cflags tre) -#LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) +LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl) LDFLAGS += $(shell $(PKG_CONFIG) --libs tre) LDFLAGS += -L$(GCCSDK_INSTALL_ENV)/lib LDFLAGS += -lpbl -liconv +ifeq ($(NETSURF_USE_OPENSSL),YES) + LDFLAGS += $(shell $(PKG_CONFIG) --static --libs openssl) +endif + ifeq ($(SUBTARGET),os3) LDFLAGS += -lamiga -lm -else - LDFLAGS += -lpthread endif EXETARGET := NetSurf commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=ac46ecbc1c2e756af6c... commit ac46ecbc1c2e756af6c2decfbd5e0a9d332fa781 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Small Capital Q codepoint diff --git a/frontends/amiga/font_bullet.c b/frontends/amiga/font_bullet.c index 62c2dde..0b414c2 100644 --- a/frontends/amiga/font_bullet.c +++ b/frontends/amiga/font_bullet.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 - 2016 Chris Young <chris(a)unsatisfactorysoftware.co.uk> + * Copyright 2008 - 2019 Chris Young <chris(a)unsatisfactorysoftware.co.uk> * * This file is part of NetSurf, http://www.netsurf-browser.org/ * @@ -82,7 +82,7 @@ const uint16 sc_table[] = { 0x006E, 0x0274, /* n */ 0x006F, 0x1D0F, /* o */ 0x0070, 0x1D18, /* p */ - 0x0071, 0xA7EE, /* q (proposed) (Adobe codepoint 0xF771) */ + 0x0071, 0xA7AF, /* q */ 0x0072, 0x0280, /* r */ 0x0073, 0xA731, /* s */ 0x0074, 0x1D1B, /* t */ ----------------------------------------------------------------------- Summary of changes: frontends/amiga/Makefile | 8 +++++--- frontends/amiga/font_bullet.c | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/frontends/amiga/Makefile b/frontends/amiga/Makefile index b71ae3c..421be0e 100644 --- a/frontends/amiga/Makefile +++ b/frontends/amiga/Makefile @@ -17,16 +17,18 @@ $(eval $(call feature_enabled,AMISSL,-DWITH_AMISSL -D__NO_NET_API -D__NO_NETINCL CFLAGS += -I$(GCCSDK_INSTALL_ENV)/include CFLAGS += $(shell $(PKG_CONFIG) --cflags tre) -#LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) +LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl) LDFLAGS += $(shell $(PKG_CONFIG) --libs tre) LDFLAGS += -L$(GCCSDK_INSTALL_ENV)/lib LDFLAGS += -lpbl -liconv +ifeq ($(NETSURF_USE_OPENSSL),YES) + LDFLAGS += $(shell $(PKG_CONFIG) --static --libs openssl) +endif + ifeq ($(SUBTARGET),os3) LDFLAGS += -lamiga -lm -else - LDFLAGS += -lpthread endif EXETARGET := NetSurf diff --git a/frontends/amiga/font_bullet.c b/frontends/amiga/font_bullet.c index 62c2dde..0b414c2 100644 --- a/frontends/amiga/font_bullet.c +++ b/frontends/amiga/font_bullet.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 - 2016 Chris Young <chris(a)unsatisfactorysoftware.co.uk> + * Copyright 2008 - 2019 Chris Young <chris(a)unsatisfactorysoftware.co.uk> * * This file is part of NetSurf, http://www.netsurf-browser.org/ * @@ -82,7 +82,7 @@ const uint16 sc_table[] = { 0x006E, 0x0274, /* n */ 0x006F, 0x1D0F, /* o */ 0x0070, 0x1D18, /* p */ - 0x0071, 0xA7EE, /* q (proposed) (Adobe codepoint 0xF771) */ + 0x0071, 0xA7AF, /* q */ 0x0072, 0x0280, /* r */ 0x0073, 0xA731, /* s */ 0x0074, 0x1D1B, /* t */ -- NetSurf Browser

3 years, 11 months

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netsurf: branch master updated. release/3.8-108-g35dbf07

by NetSurf Browser Project

Gitweb links: ...log http://git.netsurf-browser.org/netsurf.git/shortlog/35dbf07440cb6c5c26e1d... ...commit http://git.netsurf-browser.org/netsurf.git/commit/35dbf07440cb6c5c26e1dbe... ...tree http://git.netsurf-browser.org/netsurf.git/tree/35dbf07440cb6c5c26e1dbe2f... The branch, master has been updated via 35dbf07440cb6c5c26e1dbe2f7cd83ad95b745e1 (commit) via 178d4bc25c0fe781f955b32f0056cf1723c39481 (commit) via 0a72449f4bf189cd2fb9e69d72fe582420957a21 (commit) from 7c9066b49faed1a4f614a4f2a3f4f6462b377d25 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=35dbf07440cb6c5c26e... commit 35dbf07440cb6c5c26e1dbe2f7cd83ad95b745e1 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Add AmiSSL requirement diff --git a/frontends/amiga/pkg/netsurf_os3.readme b/frontends/amiga/pkg/netsurf_os3.readme index 66774e6..0b31275 100644 --- a/frontends/amiga/pkg/netsurf_os3.readme +++ b/frontends/amiga/pkg/netsurf_os3.readme @@ -3,7 +3,7 @@ Uploader: chris(a)unsatisfactorysoftware.co.uk (Chris Young) Author: NetSurf contributors (OS4 port by Chris Young) Type: comm/www Version: 3.9 BETA -Requires: dev/misc/guigfxlib.lha +Requires: dev/misc/guigfxlib.lha util/libs/AmiSSL-4.3.lha Architecture: m68k-amigaos >= 3.5.0 This is NetSurf 3.9 BETA for AmigaOS 3. commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=178d4bc25c0fe781f95... commit 178d4bc25c0fe781f955b32f0056cf1723c39481 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Fix some bsdsocket.library usage NetSurf now builds against libcurl-AmiSSL diff --git a/content/urldb.c b/content/urldb.c index c4a5a6b..d93cc58 100644 --- a/content/urldb.c +++ b/content/urldb.c @@ -116,6 +116,11 @@ #include "content/content.h" #include "content/urldb.h" +#ifdef WITH_AMISSL +/* AmiSSL needs everything to be using bsdsocket directly to avoid conflicts */ +#include <proto/bsdsocket.h> +#endif + /** * cookie entry. * diff --git a/frontends/amiga/gui.c b/frontends/amiga/gui.c index ae99450..2c84d4d 100644 --- a/frontends/amiga/gui.c +++ b/frontends/amiga/gui.c @@ -40,6 +40,12 @@ #include <proto/utility.h> #include <proto/wb.h> +#ifdef WITH_AMISSL +/* AmiSSL needs everything to use bsdsocket.library directly to avoid problems */ +#include <proto/bsdsocket.h> +#define waitselect WaitSelect +#endif + /* Other OS includes */ #include <datatypes/textclass.h> #include <devices/inputevent.h> commitdiff http://git.netsurf-browser.org/netsurf.git/commit/?id=0a72449f4bf189cd2fb... commit 0a72449f4bf189cd2fb9e69d72fe582420957a21 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Allow for building against AmiSSL instead of OpenSSL diff --git a/frontends/amiga/Makefile b/frontends/amiga/Makefile index 8584922..b71ae3c 100644 --- a/frontends/amiga/Makefile +++ b/frontends/amiga/Makefile @@ -12,11 +12,12 @@ endif $(eval $(call feature_enabled,AMIGA_ICON,-DWITH_AMIGA_ICON,,Amiga icon)) $(eval $(call feature_enabled,AMIGA_DATATYPES,-DWITH_AMIGA_DATATYPES,,DataTypes)) +$(eval $(call feature_enabled,AMISSL,-DWITH_AMISSL -D__NO_NET_API -D__NO_NETINCLUDE_ERRNO -I$(GCCSDK_INSTALL_ENV)/netinclude,-lamisslauto,AmiSSL)) CFLAGS += -I$(GCCSDK_INSTALL_ENV)/include CFLAGS += $(shell $(PKG_CONFIG) --cflags tre) -LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) +#LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) LDFLAGS += $(shell $(PKG_CONFIG) --libs tre) LDFLAGS += -L$(GCCSDK_INSTALL_ENV)/lib @@ -24,6 +25,8 @@ LDFLAGS += -lpbl -liconv ifeq ($(SUBTARGET),os3) LDFLAGS += -lamiga -lm +else + LDFLAGS += -lpthread endif EXETARGET := NetSurf diff --git a/frontends/amiga/Makefile.defaults b/frontends/amiga/Makefile.defaults index f19d6e3..2d5cec7 100644 --- a/frontends/amiga/Makefile.defaults +++ b/frontends/amiga/Makefile.defaults @@ -6,6 +6,12 @@ # Valid options: YES, NO NETSURF_USE_LIBICONV_PLUG := NO +# Use AmiSSL for secure connections. +# Either this or NETSURF_USE_OPENSSL should be specified, not both. +# libcurl must have been built against the same library. +# Valid options: YES, NO +NETSURF_USE_AMISSL := NO + # Enable NetSurf's use of librosprite for displaying RISC OS Sprites # Valid options: YES, NO, AUTO NETSURF_USE_ROSPRITE := NO @@ -30,3 +36,9 @@ NETSURF_FS_BACKING_STORE := YES # Optimisation levels CFLAGS += -fomit-frame-pointer -gstabs +# Target-specific +ifeq ($(SUBTARGET),os3) + NETSURF_USE_OPENSSL := NO + NETSURF_USE_AMISSL := YES +endif + ----------------------------------------------------------------------- Summary of changes: content/urldb.c | 5 +++++ frontends/amiga/Makefile | 5 ++++- frontends/amiga/Makefile.defaults | 12 ++++++++++++ frontends/amiga/gui.c | 6 ++++++ frontends/amiga/pkg/netsurf_os3.readme | 2 +- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/content/urldb.c b/content/urldb.c index c4a5a6b..d93cc58 100644 --- a/content/urldb.c +++ b/content/urldb.c @@ -116,6 +116,11 @@ #include "content/content.h" #include "content/urldb.h" +#ifdef WITH_AMISSL +/* AmiSSL needs everything to be using bsdsocket directly to avoid conflicts */ +#include <proto/bsdsocket.h> +#endif + /** * cookie entry. * diff --git a/frontends/amiga/Makefile b/frontends/amiga/Makefile index 8584922..b71ae3c 100644 --- a/frontends/amiga/Makefile +++ b/frontends/amiga/Makefile @@ -12,11 +12,12 @@ endif $(eval $(call feature_enabled,AMIGA_ICON,-DWITH_AMIGA_ICON,,Amiga icon)) $(eval $(call feature_enabled,AMIGA_DATATYPES,-DWITH_AMIGA_DATATYPES,,DataTypes)) +$(eval $(call feature_enabled,AMISSL,-DWITH_AMISSL -D__NO_NET_API -D__NO_NETINCLUDE_ERRNO -I$(GCCSDK_INSTALL_ENV)/netinclude,-lamisslauto,AmiSSL)) CFLAGS += -I$(GCCSDK_INSTALL_ENV)/include CFLAGS += $(shell $(PKG_CONFIG) --cflags tre) -LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) +#LDFLAGS += $(shell $(PKG_CONFIG) --static --libs libcurl openssl) LDFLAGS += $(shell $(PKG_CONFIG) --libs tre) LDFLAGS += -L$(GCCSDK_INSTALL_ENV)/lib @@ -24,6 +25,8 @@ LDFLAGS += -lpbl -liconv ifeq ($(SUBTARGET),os3) LDFLAGS += -lamiga -lm +else + LDFLAGS += -lpthread endif EXETARGET := NetSurf diff --git a/frontends/amiga/Makefile.defaults b/frontends/amiga/Makefile.defaults index f19d6e3..2d5cec7 100644 --- a/frontends/amiga/Makefile.defaults +++ b/frontends/amiga/Makefile.defaults @@ -6,6 +6,12 @@ # Valid options: YES, NO NETSURF_USE_LIBICONV_PLUG := NO +# Use AmiSSL for secure connections. +# Either this or NETSURF_USE_OPENSSL should be specified, not both. +# libcurl must have been built against the same library. +# Valid options: YES, NO +NETSURF_USE_AMISSL := NO + # Enable NetSurf's use of librosprite for displaying RISC OS Sprites # Valid options: YES, NO, AUTO NETSURF_USE_ROSPRITE := NO @@ -30,3 +36,9 @@ NETSURF_FS_BACKING_STORE := YES # Optimisation levels CFLAGS += -fomit-frame-pointer -gstabs +# Target-specific +ifeq ($(SUBTARGET),os3) + NETSURF_USE_OPENSSL := NO + NETSURF_USE_AMISSL := YES +endif + diff --git a/frontends/amiga/gui.c b/frontends/amiga/gui.c index ae99450..2c84d4d 100644 --- a/frontends/amiga/gui.c +++ b/frontends/amiga/gui.c @@ -40,6 +40,12 @@ #include <proto/utility.h> #include <proto/wb.h> +#ifdef WITH_AMISSL +/* AmiSSL needs everything to use bsdsocket.library directly to avoid problems */ +#include <proto/bsdsocket.h> +#define waitselect WaitSelect +#endif + /* Other OS includes */ #include <datatypes/textclass.h> #include <devices/inputevent.h> diff --git a/frontends/amiga/pkg/netsurf_os3.readme b/frontends/amiga/pkg/netsurf_os3.readme index 66774e6..0b31275 100644 --- a/frontends/amiga/pkg/netsurf_os3.readme +++ b/frontends/amiga/pkg/netsurf_os3.readme @@ -3,7 +3,7 @@ Uploader: chris(a)unsatisfactorysoftware.co.uk (Chris Young) Author: NetSurf contributors (OS4 port by Chris Young) Type: comm/www Version: 3.9 BETA -Requires: dev/misc/guigfxlib.lha +Requires: dev/misc/guigfxlib.lha util/libs/AmiSSL-4.3.lha Architecture: m68k-amigaos >= 3.5.0 This is NetSurf 3.9 BETA for AmigaOS 3. -- NetSurf Browser

3 years, 11 months

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toolchains: branch master updated. 41fa38327c9f58f26ada8834820f9150f2a09519

by NetSurf Browser Project

Gitweb links: ...log http://git.netsurf-browser.org/toolchains.git/shortlog/41fa38327c9f58f26a... ...commit http://git.netsurf-browser.org/toolchains.git/commit/41fa38327c9f58f26ada... ...tree http://git.netsurf-browser.org/toolchains.git/tree/41fa38327c9f58f26ada88... The branch, master has been updated via 41fa38327c9f58f26ada8834820f9150f2a09519 (commit) via 3c5877779e696072d761e9d1ff438664c6da22be (commit) via 31ffd797f585e38d8313bb96dbf098946aff0b50 (commit) via 6614e94f4b127679005f943b99fa1251b227671e (commit) via f09efd8d5bd224867480eca99ca30881d99b0156 (commit) via 19f64e40dbedc37bb362300c028a5d74621677fa (commit) via 8204e885a4915d1d33285c417de6270c106d3db2 (commit) via 4dce591dbae6512ab6671f7274cf7a1c2727c658 (commit) from 7a20aaf7ef829cbc3abed47d20852b3112678523 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=41fa38327c9f58f2... commit 41fa38327c9f58f26ada8834820f9150f2a09519 Author: Vincent Sanders <vince(a)kyllikki.org> Commit: Vincent Sanders <vince(a)kyllikki.org> updated curl requires a later version of cares to build diff --git a/sdk/Makefile b/sdk/Makefile index e49b01c..1a7c643 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -30,7 +30,7 @@ VERSION_OPENSSL := 1.1.0j VERSION_LIBPNG := 1.6.36 VERSION_LIBJPEG := 8d VERSION_LIBJPEG_TURBO := 1.5.3 -VERSION_LIBCARES := 1.13.0 +VERSION_LIBCARES := 1.15.0 VERSION_LIBCURL := 7.64.1 VERSION_LIBGNURX := 2.5.1 VERSION_LIBPBL := 1_04 commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=3c5877779e696072... commit 3c5877779e696072d761e9d1ff438664c6da22be Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Fix ppc-amigaos libcurl 7.64.1 build diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p index 9833c94..5243fc5 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p @@ -1,11 +1,20 @@ ---- lib/amigaos.c.old 2012-10-19 21:37:45.000000000 +0100 -+++ lib/amigaos.c 2012-10-19 21:38:09.000000000 +0100 -@@ -22,7 +22,7 @@ +--- lib/amigaos.c 2019-03-25 08:42:50.000000000 +0000 ++++ lib/amigaos.c 2019-03-30 12:49:06.680985341 +0000 +@@ -24,7 +24,7 @@ - #include "curl_setup.h" + #ifdef __AMIGA__ + # include "amigaos.h" +-# if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL) ++# if 0 + # include <amitcp/socketbasetags.h> + # endif + # ifdef __libnix__ +@@ -37,7 +37,7 @@ + #include "memdebug.h" --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if defined(__AMIGA__) && !(defined(__ixemul__) || defined(__amigaos4__)) - - #include <amitcp/socketbasetags.h> + #ifdef __AMIGA__ +-#if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL) ++#if 0 + struct Library *SocketBase = NULL; + extern int errno, h_errno; diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p index 050bea7..2f62a1c 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p @@ -1,11 +1,11 @@ ---- lib/amigaos.h.old 2012-10-19 21:36:23.000000000 +0100 -+++ lib/amigaos.h 2012-10-19 21:37:26.000000000 +0100 +--- lib/amigaos.h 2019-03-25 08:42:50.000000000 +0000 ++++ lib/amigaos.h 2019-03-30 12:49:50.744493740 +0000 @@ -23,7 +23,7 @@ ***************************************************************************/ #include "curl_setup.h" --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if defined(__AMIGA__) && !(defined(__ixemul__) || defined(__amigaos4__)) +-#if defined(__AMIGA__) && defined(HAVE_BSDSOCKET_H) && !defined(USE_AMISSL) ++#if 0 bool Curl_amiga_init(); void Curl_amiga_cleanup(); diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p index 7e47a50..0e52d73 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p @@ -1,23 +1,12 @@ ---- lib/curl_setup.h.old 2012-10-19 21:58:12.000000000 +0100 -+++ lib/curl_setup.h 2012-10-19 21:59:17.000000000 +0100 -@@ -323,11 +323,15 @@ - - #ifdef __AMIGA__ - # ifndef __ixemul__ --# include <exec/types.h> --# include <exec/execbase.h> --# include <proto/exec.h> --# include <proto/dos.h> --# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) -+# ifdef __amigaos4__ -+# include <unistd.h> -+# else -+# include <exec/types.h> -+# include <exec/execbase.h> -+# include <proto/exec.h> -+# include <proto/dos.h> -+# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) -+# endif +--- lib/curl_setup.h 2019-03-30 13:44:08.576270700 +0000 ++++ lib/curl_setup.h 2019-03-30 13:44:33.011975643 +0000 +@@ -314,7 +314,8 @@ + # include <exec/execbase.h> + # include <proto/exec.h> + # include <proto/dos.h> +-# ifdef HAVE_PROTO_BSDSOCKET_H ++# define HAVE_SELECT 1 ++# if 0 + # include <proto/bsdsocket.h> /* ensure bsdsocket.library use */ + # define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) # endif - #endif - diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p b/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p index 6237496..4c9a726 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p @@ -1,26 +1,11 @@ ---- src/tool_operate.c.orig 2019-02-14 14:10:08.086190650 +0000 -+++ src/tool_operate.c 2019-02-14 14:10:04.862196063 +0000 -@@ -33,6 +33,10 @@ - # include <fabdef.h> - #endif - -+#ifdef __AMIGA__ -+#include <proto/dos.h> -+#endif -+ - #include "strcase.h" - - #define ENABLE_CURLX_PRINTF -@@ -1856,9 +1860,9 @@ - #ifdef __AMIGA__ - if(!result && outs.s_isreg && outs.filename) { +--- src/tool_operate.c 2019-03-30 12:33:41.315465662 +0000 ++++ src/tool_operate.c 2019-03-30 12:42:36.643382219 +0000 +@@ -1872,7 +1872,7 @@ static CURLcode operate_do(struct Global /* Set the url (up to 80 chars) as comment for the file */ -- if(strlen(url) > 78) -- url[79] = '\0'; -- SetComment(outs.filename, url); -+ if(strlen(urlnode->url) > 78) -+ urlnode->url[79] = '\0'; -+ /*SetComment(outs.filename, urlnode->url);*/ /* cannot get a header to include that provides this function */ + if(strlen(urlnode->url) > 78) + urlnode->url[79] = '\0'; +- SetComment(outs.filename, urlnode->url); ++ IDOS->SetComment(outs.filename, urlnode->url); } #endif commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=31ffd797f585e38d... commit 31ffd797f585e38d8313bb96dbf098946aff0b50 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Need Curl 7.64.1 for AmiSSL diff --git a/sdk/Makefile b/sdk/Makefile index d176e63..e49b01c 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -31,7 +31,7 @@ VERSION_LIBPNG := 1.6.36 VERSION_LIBJPEG := 8d VERSION_LIBJPEG_TURBO := 1.5.3 VERSION_LIBCARES := 1.13.0 -VERSION_LIBCURL := 7.64.0 +VERSION_LIBCURL := 7.64.1 VERSION_LIBGNURX := 2.5.1 VERSION_LIBPBL := 1_04 VERSION_LIBCF := CVS-20130415 commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=6614e94f4b127679... commit 6614e94f4b127679005f943b99fa1251b227671e Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> These patches shouldn't be needed with the next release of curl (>7.64.0) At least if built against AmiSSL+bsdsocket the base package will configure properly for OS3 (OS4, not so much) diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p deleted file mode 100644 index 5b6c913..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p +++ /dev/null @@ -1,11 +0,0 @@ ---- lib/amigaos.c 2014-06-11 18:52:29.000000000 +0100 -+++ lib/amigaos.c 2014-12-20 21:34:06.686013103 +0000 -@@ -22,7 +22,7 @@ - - #include "curl_setup.h" - --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if 0 - - #include <amitcp/socketbasetags.h> - diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p deleted file mode 100644 index de22d82..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p +++ /dev/null @@ -1,11 +0,0 @@ ---- lib/amigaos.h 2014-06-11 18:52:29.000000000 +0100 -+++ lib/amigaos.h 2014-12-20 21:34:20.390013061 +0000 -@@ -23,7 +23,7 @@ - ***************************************************************************/ - #include "curl_setup.h" - --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if 0 - - bool Curl_amiga_init(); - void Curl_amiga_cleanup(); diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p deleted file mode 100644 index c9b9af3..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p +++ /dev/null @@ -1,10 +0,0 @@ ---- lib/curl_setup.h 2014-08-25 22:45:11.000000000 +0100 -+++ lib/curl_setup.h 2014-12-20 21:35:26.494012868 +0000 -@@ -311,7 +311,6 @@ - # include <exec/execbase.h> - # include <proto/exec.h> - # include <proto/dos.h> --# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) - # endif - #endif - diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p deleted file mode 100644 index 7de5cba..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p +++ /dev/null @@ -1,13 +0,0 @@ ---- ./tool_getpass.c 2014-06-11 18:52:29.000000000 +0100 -+++ src/tool_getpass.c 2015-01-05 21:42:31.826011647 +0000 -@@ -24,6 +24,10 @@ - #ifndef HAVE_GETPASS_R - /* this file is only for systems without getpass_r() */ - -+#ifdef __AMIGA__ -+#undef HAVE_TERMIOS_H -+#endif -+ - #ifdef HAVE_FCNTL_H - # include <fcntl.h> - #endif diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p deleted file mode 100644 index 6237496..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p +++ /dev/null @@ -1,26 +0,0 @@ ---- src/tool_operate.c.orig 2019-02-14 14:10:08.086190650 +0000 -+++ src/tool_operate.c 2019-02-14 14:10:04.862196063 +0000 -@@ -33,6 +33,10 @@ - # include <fabdef.h> - #endif - -+#ifdef __AMIGA__ -+#include <proto/dos.h> -+#endif -+ - #include "strcase.h" - - #define ENABLE_CURLX_PRINTF -@@ -1856,9 +1860,9 @@ - #ifdef __AMIGA__ - if(!result && outs.s_isreg && outs.filename) { - /* Set the url (up to 80 chars) as comment for the file */ -- if(strlen(url) > 78) -- url[79] = '\0'; -- SetComment(outs.filename, url); -+ if(strlen(urlnode->url) > 78) -+ urlnode->url[79] = '\0'; -+ /*SetComment(outs.filename, urlnode->url);*/ /* cannot get a header to include that provides this function */ - } - #endif - commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=f09efd8d5bd22486... commit f09efd8d5bd224867480eca99ca30881d99b0156 Author: Vincent Sanders <vince(a)kyllikki.org> Commit: Vincent Sanders <vince(a)kyllikki.org> Build libcurl against AmiSSL for m68k-unknown-amigaos target diff --git a/sdk/Makefile b/sdk/Makefile index 383e842..d176e63 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -127,11 +127,11 @@ endif ifeq ($(TARGET),m68k-unknown-amigaos) SDK_ITEMS := $(addprefix $(BUILDSTEPS)/, roadshow.d libiconv.d libtre.d libpbl.d $(COMMON_SDK_ITEMS) libjpeg.d) EXTRAARGS_LIBCARES := --disable-shared --without-random - EXTRAARGS_LIBCURL := --disable-ntlm-wb --without-random --disable-threaded-resolver --with-ssl --with-zlib + EXTRAARGS_LIBCURL := --disable-ntlm-wb --without-random --disable-threaded-resolver --with-amissl --with-zlib --disable-rt LIBICONV_ENV := CFLAGS="-DPATH_MAX=1024" LIBJPEG_ENV := LDFLAGS="-lm" LIBJPEG_TURBO_ENV := LDFLAGS="-lm" - LIBCURL_ENV := LIBS="-lm" + LIBCURL_ENV := CFLAGS="-I$(GCCSDK_INSTALL_ENV)/netinclude -D__NO_NET_API" LIBS="-lm" endif ifeq ($(SDK_ITEMS),) commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=19f64e40dbedc37b... commit 19f64e40dbedc37bb362300c028a5d74621677fa Author: Vincent Sanders <vince(a)kyllikki.org> Commit: Vincent Sanders <vince(a)kyllikki.org> Don't build OpenSSL for m68k-amigaos skip the build but mark the build step as complete because Curl needs it. Issues: Curl won't see AmiSSL as the includes alone are not enough to trick it. Creating dummy libssl.a libcrypto.a nearly works but still chokes as the test programs don't include anything so the AmiSSL inlines don't get opened. Solution might be to build a dummy libssl.a which redirects the needed functions. There's an issue with amissl/inline.h with the latest includes (hack #define it so it doesn't try - may cause other problems later but this is not where the troublesome SSL_connect() is defined) diff --git a/sdk/Makefile b/sdk/Makefile index e546e10..383e842 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -350,8 +350,10 @@ $(SOURCEDIR)/pbl_$(VERSION_LIBPBL).tar.gz: # OpenSSL $(BUILDSTEPS)/openssl.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/zlib.d $(BUILDSTEPS)/openssl-src.d +ifneq ($(TARGET),m68k-unknown-amigaos) cd $(BUILDDIR)/openssl/openssl-$(VERSION_OPENSSL) && $(env) ./Configure --prefix=$(GCCSDK_INSTALL_ENV) $(TARGET) no-shared no-threads $(EXTRAARGS_OPENSSL) cd $(BUILDDIR)/openssl/openssl-$(VERSION_OPENSSL) && $(env) make install +endif touch $@ # prepare the openssl source tree commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=8204e885a4915d1d... commit 8204e885a4915d1d33285c417de6270c106d3db2 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Install the Roadshow SDK into netinclude This is a modified copy of the SDK, partly because the official download is buried behind a form and can't be downloaded directly: netinclude/inline/* are the corrected ones netinclude/errno.h has been removed source_code has been removed diff --git a/sdk/Makefile b/sdk/Makefile index 70e37d0..e546e10 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -125,7 +125,7 @@ ifeq ($(TARGET),i686-w64-mingw32) endif ifeq ($(TARGET),m68k-unknown-amigaos) - SDK_ITEMS := $(addprefix $(BUILDSTEPS)/, libiconv.d libtre.d libpbl.d $(COMMON_SDK_ITEMS) libjpeg.d) + SDK_ITEMS := $(addprefix $(BUILDSTEPS)/, roadshow.d libiconv.d libtre.d libpbl.d $(COMMON_SDK_ITEMS) libjpeg.d) EXTRAARGS_LIBCARES := --disable-shared --without-random EXTRAARGS_LIBCURL := --disable-ntlm-wb --without-random --disable-threaded-resolver --with-ssl --with-zlib LIBICONV_ENV := CFLAGS="-DPATH_MAX=1024" @@ -302,6 +302,20 @@ $(BUILDSTEPS)/freetype-src.d: $(BUILDSTEPS)/sourcedir.d $(SOURCEDIR)/freetype-$( $(SOURCEDIR)/freetype-$(VERSION_FREETYPE).tar.bz2: $(FETCHSRC) sdk $(subst $(SOURCEDIR)/,,$@) "http://download.savannah.gnu.org/releases/freetype/freetype-$(VERSION_FRE..." $@ +# amiga roadshow sdk +$(BUILDSTEPS)/roadshow.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/roadshow-src.d + mkdir -p $(BUILDDIR)/Roadshow-SDK + lha xw=$(BUILDDIR)/Roadshow-SDK $(SOURCEDIR)/Roadshow-SDK-NS.lha + mkdir -p $(GCCSDK_INSTALL_ENV)/netinclude + cp -r $(BUILDDIR)/Roadshow-SDK/SDK/netinclude/* $(GCCSDK_INSTALL_ENV)/netinclude/ + touch $@ + +$(BUILDSTEPS)/roadshow-src.d: $(BUILDSTEPS)/sourcedir.d $(SOURCEDIR)/Roadshow-SDK-NS.lha + touch $@ + +$(SOURCEDIR)/Roadshow-SDK-NS.lha: + $(FETCHSRC) sdk $(subst $(SOURCEDIR)/,,$@) "https://github.com/chris-y/curl/releases/download/curl-7_64_0-amissl/Road..." $@ + # regex $(BUILDSTEPS)/libtre.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/libtre-src.d mkdir -p $(BUILDDIR)/libtre commitdiff http://git.netsurf-browser.org/toolchains.git/commit/?id=4dce591dbae6512a... commit 4dce591dbae6512ab6671f7274cf7a1c2727c658 Author: Chris Young <chris(a)unsatisfactorysoftware.co.uk> Commit: Vincent Sanders <vince(a)kyllikki.org> Add AmiSSL 4.2 SDK to m68k-amigaos build v4.3 has compatibility issues which means that SDK won't work with future versions, whereas 4.2 will. NDK inline/macros.h suitable for use with AmiSSL diff --git a/m68k-unknown-amigaos/Makefile b/m68k-unknown-amigaos/Makefile index f7e1534..dd171af 100644 --- a/m68k-unknown-amigaos/Makefile +++ b/m68k-unknown-amigaos/Makefile @@ -36,6 +36,10 @@ UPSTREAM_OPENURL_VERSION := 7.16 UPSTREAM_OPENURL_TARBALL := openurl-$(UPSTREAM_OPENURL_VERSION) UPSTREAM_OPENURL_URI := https://github.com/jens-maus/libopenurl/archive/$(UPSTREAM_OPENURL_VERSIO... +UPSTREAM_AMISSL_VERSION := 4.2 +UPSTREAM_AMISSL_TARBALL := AmiSSL-$(UPSTREAM_AMISSL_VERSION).lha +UPSTREAM_AMISSL_URI := https://github.com/jens-maus/amissl/releases/download/$(UPSTREAM_AMISSL_V... + UPSTREAM_GUIGFX_TARBALL := guigfxlib.lha UPSTREAM_GUIGFX_URI := http://neoscientists.org/~bifat/binarydistillery/$(UPSTREAM_GUIGFX_TARBALL) @@ -120,7 +124,7 @@ $(BUILDSTEPS)/clib2-src.d: $(SOURCESDIR)/$(UPSTREAM_CLIB2_TARBALL) # Rules to install the NDK ### -$(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTREAM_OPENURL_TARBALL) $(SOURCESDIR)/$(UPSTREAM_GUIGFX_TARBALL) $(SOURCESDIR)/$(UPSTREAM_RENDER_TARBALL) $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) +$(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTREAM_OPENURL_TARBALL) $(SOURCESDIR)/$(UPSTREAM_GUIGFX_TARBALL) $(SOURCESDIR)/$(UPSTREAM_RENDER_TARBALL) $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) $(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL) mkdir -p $(PREFIX)/$(TARGET_NAME) tar -C $(PREFIX)/$(TARGET_NAME) --strip-components=2 -xjf $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) for p in `ls $(RECIPES)/patches/ndk/*.p` ; do patch -d $(PREFIX)/$(TARGET_NAME) -p0 <$$p ; done @@ -138,6 +142,10 @@ $(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTR mkdir -p $(BUILDDIR)/codesets lha xw=$(BUILDDIR)/codesets $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) cp -r $(BUILDDIR)/codesets/codesets/Developer/include/* $(PREFIX)/$(TARGET_NAME)/sys-include/ + mkdir -p $(BUILDDIR)/AmiSSL + lha xw=$(BUILDDIR)/AmiSSL $(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL) + cp -r $(BUILDDIR)/AmiSSL/AmiSSL/Developer/include/* $(PREFIX)/$(TARGET_NAME)/sys-include/ + cp -r $(BUILDDIR)/AmiSSL/AmiSSL/Developer/lib/AmigaOS3/* $(PREFIX)/$(TARGET_NAME)/lib/ touch $@ ### @@ -263,6 +271,9 @@ $(SOURCESDIR)/$(UPSTREAM_BISON_TARBALL): $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL): wget -q -O $@ $(UPSTREAM_CODESETS_URI) +$(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL): + wget -q -O $@ $(UPSTREAM_AMISSL_URI) + ### # Rule to create buildsteps dir ### diff --git a/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h b/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h new file mode 100644 index 0000000..2a07ae6 --- /dev/null +++ b/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h @@ -0,0 +1,1749 @@ +#ifndef __INLINE_MACROS_H +#define __INLINE_MACROS_H + +/* + General macros for Amiga function calls. Not all the possibilities have + been created - only the ones which exist in OS 3.1. Third party libraries + and future versions of AmigaOS will maybe need some new ones... + + LPX - functions that take X arguments. + + Modifiers (variations are possible): + NR - no return (void), + A4, A5 - "a4" or "a5" is used as one of the arguments, + UB - base will be given explicitly by user (see cia.resource). + FP - one of the parameters has type "pointer to function". + FR - the return type is a "pointer to function". + + "bt" arguments are not used - they are provided for backward compatibility + only. +*/ + +#ifndef __INLINE_STUB_H +#include <inline/stubs.h> +#endif + +#define LP0(offs, rt, name, bt, bn) \ +({ \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP0FR(offs, rt, name, bt, bn, fpr) \ +({ \ + typedef fpr; \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP0NR(offs, name, bt, bn) \ +({ \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FR(offs, rt, name, t1, v1, r1, bt, bn, fpr) \ +({ \ + typedef fpr; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FPFR(offs, rt, name, t1, v1, r1, bt, bn, fpt, fpr) \ +({ \ + typedef fpr; \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1NR(offs, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only graphics.library/AttemptLockLayerRom() */ +#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */ +#define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/Supervisor() */ +#define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1NRFP(offs, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only cia.resource/AbleICR() and cia.resource/SetICR() */ +#define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only dos.library/InternalUnLoadSeg() */ +#define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2FPFR(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt, fpr) \ +({ \ + typedef fpr; \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2NRFP(offs, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only cia.resource/AddICRVector() */ +#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only cia.resource/RemICRVector() */ +#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/SetFunction() */ +#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3FP2(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3FP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/SetCollision() */ +#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3NRFP2(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3NRFP3(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP4NRFP3(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/RawDoFmt() */ +#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP4FP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt1, fpt2, fpt3, fpt4) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + typedef fpt4; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP5NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +#define LP5NRA5(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/MakeLibrary() */ +#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only reqtools.library/XXX() */ +#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP6A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +#define LP6FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP7NRFP6(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, fpt1, fpt2, fpt3, fpt4, fpt5, fpt6) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + typedef fpt4; \ + typedef fpt5; \ + typedef fpt6; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only workbench.library/AddAppIconA() */ +#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* Would you believe that there really are beasts that need more than 7 + arguments? :-) */ + +/* For example intuition.library/AutoRequest() */ +#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* For example intuition.library/ModifyProp() */ +#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP8A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP8NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* For example layers.library/CreateUpfrontHookLayer() */ +#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* For example intuition.library/NewModifyProp() */ +#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP9A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP9NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* Kriton Kyrimis <kyrimis(a)cti.gr> says CyberGraphics needs the following */ +#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/BltMaskBitMapRastPort() */ +#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP10A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/BltBitMap() */ +#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + t11 _##name##_v11 = (v11); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + register t11 _n11 __asm(#r11) = _##name##_v11; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#endif /* __INLINE_MACROS_H */ + ----------------------------------------------------------------------- Summary of changes: m68k-unknown-amigaos/Makefile | 13 +- .../recipes/files/ndk/sys-include/inline/macros.h | 1749 ++++++++++++++++++++ sdk/Makefile | 26 +- .../libcurl/m68k-unknown-amigaos/lib.amigaos.c.p | 11 - .../libcurl/m68k-unknown-amigaos/lib.amigaos.h.p | 11 - .../m68k-unknown-amigaos/lib.curl_setup.h.p | 10 - .../m68k-unknown-amigaos/src.tool_getpass.c.p | 13 - .../m68k-unknown-amigaos/src.tool_operate.c.p | 26 - .../patches/libcurl/ppc-amigaos/lib.amigaos.c.p | 25 +- .../patches/libcurl/ppc-amigaos/lib.amigaos.h.p | 8 +- .../patches/libcurl/ppc-amigaos/lib.curl_setup.h.p | 33 +- .../libcurl/ppc-amigaos/src.tool_operate.c.p | 29 +- 12 files changed, 1821 insertions(+), 133 deletions(-) create mode 100644 m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h delete mode 100644 sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p delete mode 100644 sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p delete mode 100644 sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p delete mode 100644 sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p delete mode 100644 sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p diff --git a/m68k-unknown-amigaos/Makefile b/m68k-unknown-amigaos/Makefile index f7e1534..dd171af 100644 --- a/m68k-unknown-amigaos/Makefile +++ b/m68k-unknown-amigaos/Makefile @@ -36,6 +36,10 @@ UPSTREAM_OPENURL_VERSION := 7.16 UPSTREAM_OPENURL_TARBALL := openurl-$(UPSTREAM_OPENURL_VERSION) UPSTREAM_OPENURL_URI := https://github.com/jens-maus/libopenurl/archive/$(UPSTREAM_OPENURL_VERSIO... +UPSTREAM_AMISSL_VERSION := 4.2 +UPSTREAM_AMISSL_TARBALL := AmiSSL-$(UPSTREAM_AMISSL_VERSION).lha +UPSTREAM_AMISSL_URI := https://github.com/jens-maus/amissl/releases/download/$(UPSTREAM_AMISSL_V... + UPSTREAM_GUIGFX_TARBALL := guigfxlib.lha UPSTREAM_GUIGFX_URI := http://neoscientists.org/~bifat/binarydistillery/$(UPSTREAM_GUIGFX_TARBALL) @@ -120,7 +124,7 @@ $(BUILDSTEPS)/clib2-src.d: $(SOURCESDIR)/$(UPSTREAM_CLIB2_TARBALL) # Rules to install the NDK ### -$(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTREAM_OPENURL_TARBALL) $(SOURCESDIR)/$(UPSTREAM_GUIGFX_TARBALL) $(SOURCESDIR)/$(UPSTREAM_RENDER_TARBALL) $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) +$(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTREAM_OPENURL_TARBALL) $(SOURCESDIR)/$(UPSTREAM_GUIGFX_TARBALL) $(SOURCESDIR)/$(UPSTREAM_RENDER_TARBALL) $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) $(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL) mkdir -p $(PREFIX)/$(TARGET_NAME) tar -C $(PREFIX)/$(TARGET_NAME) --strip-components=2 -xjf $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) for p in `ls $(RECIPES)/patches/ndk/*.p` ; do patch -d $(PREFIX)/$(TARGET_NAME) -p0 <$$p ; done @@ -138,6 +142,10 @@ $(BUILDSTEPS)/ndk.d: $(SOURCESDIR)/$(UPSTREAM_NDK_TARBALL) $(SOURCESDIR)/$(UPSTR mkdir -p $(BUILDDIR)/codesets lha xw=$(BUILDDIR)/codesets $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL) cp -r $(BUILDDIR)/codesets/codesets/Developer/include/* $(PREFIX)/$(TARGET_NAME)/sys-include/ + mkdir -p $(BUILDDIR)/AmiSSL + lha xw=$(BUILDDIR)/AmiSSL $(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL) + cp -r $(BUILDDIR)/AmiSSL/AmiSSL/Developer/include/* $(PREFIX)/$(TARGET_NAME)/sys-include/ + cp -r $(BUILDDIR)/AmiSSL/AmiSSL/Developer/lib/AmigaOS3/* $(PREFIX)/$(TARGET_NAME)/lib/ touch $@ ### @@ -263,6 +271,9 @@ $(SOURCESDIR)/$(UPSTREAM_BISON_TARBALL): $(SOURCESDIR)/$(UPSTREAM_CODESETS_TARBALL): wget -q -O $@ $(UPSTREAM_CODESETS_URI) +$(SOURCESDIR)/$(UPSTREAM_AMISSL_TARBALL): + wget -q -O $@ $(UPSTREAM_AMISSL_URI) + ### # Rule to create buildsteps dir ### diff --git a/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h b/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h new file mode 100644 index 0000000..2a07ae6 --- /dev/null +++ b/m68k-unknown-amigaos/recipes/files/ndk/sys-include/inline/macros.h @@ -0,0 +1,1749 @@ +#ifndef __INLINE_MACROS_H +#define __INLINE_MACROS_H + +/* + General macros for Amiga function calls. Not all the possibilities have + been created - only the ones which exist in OS 3.1. Third party libraries + and future versions of AmigaOS will maybe need some new ones... + + LPX - functions that take X arguments. + + Modifiers (variations are possible): + NR - no return (void), + A4, A5 - "a4" or "a5" is used as one of the arguments, + UB - base will be given explicitly by user (see cia.resource). + FP - one of the parameters has type "pointer to function". + FR - the return type is a "pointer to function". + + "bt" arguments are not used - they are provided for backward compatibility + only. +*/ + +#ifndef __INLINE_STUB_H +#include <inline/stubs.h> +#endif + +#define LP0(offs, rt, name, bt, bn) \ +({ \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP0FR(offs, rt, name, bt, bn, fpr) \ +({ \ + typedef fpr; \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP0NR(offs, name, bt, bn) \ +({ \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP1(offs, rt, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FR(offs, rt, name, t1, v1, r1, bt, bn, fpr) \ +({ \ + typedef fpr; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1FPFR(offs, rt, name, t1, v1, r1, bt, bn, fpt, fpr) \ +({ \ + typedef fpr; \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1NR(offs, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only graphics.library/AttemptLockLayerRom() */ +#define LP1A5(offs, rt, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/LockLayerRom() and graphics.library/UnlockLayerRom() */ +#define LP1NRA5(offs, name, t1, v1, r1, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/Supervisor() */ +#define LP1A5FP(offs, rt, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP1NRFP(offs, name, t1, v1, r1, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP2(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2NR(offs, name, t1, v1, r1, t2, v2, r2, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only cia.resource/AbleICR() and cia.resource/SetICR() */ +#define LP2UB(offs, rt, name, t1, v1, r1, t2, v2, r2) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only dos.library/InternalUnLoadSeg() */ +#define LP2FP(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2FPFR(offs, rt, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt, fpr) \ +({ \ + typedef fpr; \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP2NRFP(offs, name, t1, v1, r1, t2, v2, r2, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only cia.resource/AddICRVector() */ +#define LP3UB(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only cia.resource/RemICRVector() */ +#define LP3NRUB(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/SetFunction() */ +#define LP3FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3FP2(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP3FP3(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/SetCollision() */ +#define LP3NRFP(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3NRFP2(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP3NRFP3(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP4NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP4NRFP3(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt1, fpt2, fpt3) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/RawDoFmt() */ +#define LP4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP4FP4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, bt, bn, fpt1, fpt2, fpt3, fpt4) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + typedef fpt4; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP5NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +#define LP5NRA5(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a5\n\tjsr a6@(-"#offs":W)\n\texg d7,a5" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only exec.library/MakeLibrary() */ +#define LP5FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only reqtools.library/XXX() */ +#define LP5A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP5A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP6A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +#define LP6FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP6A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP7NRFP6(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, fpt1, fpt2, fpt3, fpt4, fpt5, fpt6) \ +({ \ + typedef fpt1; \ + typedef fpt2; \ + typedef fpt3; \ + typedef fpt4; \ + typedef fpt5; \ + typedef fpt6; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +/* Only workbench.library/AddAppIconA() */ +#define LP7A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7A4FP(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn, fpt) \ +({ \ + typedef fpt; \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP7NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* Would you believe that there really are beasts that need more than 7 + arguments? :-) */ + +/* For example intuition.library/AutoRequest() */ +#define LP8(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* For example intuition.library/ModifyProp() */ +#define LP8NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP8A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP8NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* For example layers.library/CreateUpfrontHookLayer() */ +#define LP9(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* For example intuition.library/NewModifyProp() */ +#define LP9NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP9A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#define LP9NRA4(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9) \ + : "fp0", "fp1", "cc", "memory"); \ + }; \ +}) + +/* Kriton Kyrimis <kyrimis(a)cti.gr> says CyberGraphics needs the following */ +#define LP10(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/BltMaskBitMapRastPort() */ +#define LP10NR(offs, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + { \ + register int _d0 __asm("d0"); \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_d0), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + } \ +}) + +#define LP10A4(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + __asm volatile ("exg d7,a4\n\tjsr a6@(-"#offs":W)\n\texg d7,a4" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +/* Only graphics.library/BltBitMap() */ +#define LP11(offs, rt, name, t1, v1, r1, t2, v2, r2, t3, v3, r3, t4, v4, r4, t5, v5, r5, t6, v6, r6, t7, v7, r7, t8, v8, r8, t9, v9, r9, t10, v10, r10, t11, v11, r11, bt, bn) \ +({ \ + t1 _##name##_v1 = (v1); \ + t2 _##name##_v2 = (v2); \ + t3 _##name##_v3 = (v3); \ + t4 _##name##_v4 = (v4); \ + t5 _##name##_v5 = (v5); \ + t6 _##name##_v6 = (v6); \ + t7 _##name##_v7 = (v7); \ + t8 _##name##_v8 = (v8); \ + t9 _##name##_v9 = (v9); \ + t10 _##name##_v10 = (v10); \ + t11 _##name##_v11 = (v11); \ + rt _##name##_re2 = \ + ({ \ + register int _d1 __asm("d1"); \ + register int _a0 __asm("a0"); \ + register int _a1 __asm("a1"); \ + register rt _##name##_re __asm("d0"); \ + register void *const _##name##_bn __asm("a6") = (bn); \ + register t1 _n1 __asm(#r1) = _##name##_v1; \ + register t2 _n2 __asm(#r2) = _##name##_v2; \ + register t3 _n3 __asm(#r3) = _##name##_v3; \ + register t4 _n4 __asm(#r4) = _##name##_v4; \ + register t5 _n5 __asm(#r5) = _##name##_v5; \ + register t6 _n6 __asm(#r6) = _##name##_v6; \ + register t7 _n7 __asm(#r7) = _##name##_v7; \ + register t8 _n8 __asm(#r8) = _##name##_v8; \ + register t9 _n9 __asm(#r9) = _##name##_v9; \ + register t10 _n10 __asm(#r10) = _##name##_v10; \ + register t11 _n11 __asm(#r11) = _##name##_v11; \ + __asm volatile ("jsr a6@(-"#offs":W)" \ + : "=r" (_##name##_re), "=r" (_d1), "=r" (_a0), "=r" (_a1) \ + : "r" (_##name##_bn), "rf"(_n1), "rf"(_n2), "rf"(_n3), "rf"(_n4), "rf"(_n5), "rf"(_n6), "rf"(_n7), "rf"(_n8), "rf"(_n9), "rf"(_n10), "rf"(_n11) \ + : "fp0", "fp1", "cc", "memory"); \ + _##name##_re; \ + }); \ + _##name##_re2; \ +}) + +#endif /* __INLINE_MACROS_H */ + diff --git a/sdk/Makefile b/sdk/Makefile index 70e37d0..1a7c643 100644 --- a/sdk/Makefile +++ b/sdk/Makefile @@ -30,8 +30,8 @@ VERSION_OPENSSL := 1.1.0j VERSION_LIBPNG := 1.6.36 VERSION_LIBJPEG := 8d VERSION_LIBJPEG_TURBO := 1.5.3 -VERSION_LIBCARES := 1.13.0 -VERSION_LIBCURL := 7.64.0 +VERSION_LIBCARES := 1.15.0 +VERSION_LIBCURL := 7.64.1 VERSION_LIBGNURX := 2.5.1 VERSION_LIBPBL := 1_04 VERSION_LIBCF := CVS-20130415 @@ -125,13 +125,13 @@ ifeq ($(TARGET),i686-w64-mingw32) endif ifeq ($(TARGET),m68k-unknown-amigaos) - SDK_ITEMS := $(addprefix $(BUILDSTEPS)/, libiconv.d libtre.d libpbl.d $(COMMON_SDK_ITEMS) libjpeg.d) + SDK_ITEMS := $(addprefix $(BUILDSTEPS)/, roadshow.d libiconv.d libtre.d libpbl.d $(COMMON_SDK_ITEMS) libjpeg.d) EXTRAARGS_LIBCARES := --disable-shared --without-random - EXTRAARGS_LIBCURL := --disable-ntlm-wb --without-random --disable-threaded-resolver --with-ssl --with-zlib + EXTRAARGS_LIBCURL := --disable-ntlm-wb --without-random --disable-threaded-resolver --with-amissl --with-zlib --disable-rt LIBICONV_ENV := CFLAGS="-DPATH_MAX=1024" LIBJPEG_ENV := LDFLAGS="-lm" LIBJPEG_TURBO_ENV := LDFLAGS="-lm" - LIBCURL_ENV := LIBS="-lm" + LIBCURL_ENV := CFLAGS="-I$(GCCSDK_INSTALL_ENV)/netinclude -D__NO_NET_API" LIBS="-lm" endif ifeq ($(SDK_ITEMS),) @@ -302,6 +302,20 @@ $(BUILDSTEPS)/freetype-src.d: $(BUILDSTEPS)/sourcedir.d $(SOURCEDIR)/freetype-$( $(SOURCEDIR)/freetype-$(VERSION_FREETYPE).tar.bz2: $(FETCHSRC) sdk $(subst $(SOURCEDIR)/,,$@) "http://download.savannah.gnu.org/releases/freetype/freetype-$(VERSION_FRE..." $@ +# amiga roadshow sdk +$(BUILDSTEPS)/roadshow.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/roadshow-src.d + mkdir -p $(BUILDDIR)/Roadshow-SDK + lha xw=$(BUILDDIR)/Roadshow-SDK $(SOURCEDIR)/Roadshow-SDK-NS.lha + mkdir -p $(GCCSDK_INSTALL_ENV)/netinclude + cp -r $(BUILDDIR)/Roadshow-SDK/SDK/netinclude/* $(GCCSDK_INSTALL_ENV)/netinclude/ + touch $@ + +$(BUILDSTEPS)/roadshow-src.d: $(BUILDSTEPS)/sourcedir.d $(SOURCEDIR)/Roadshow-SDK-NS.lha + touch $@ + +$(SOURCEDIR)/Roadshow-SDK-NS.lha: + $(FETCHSRC) sdk $(subst $(SOURCEDIR)/,,$@) "https://github.com/chris-y/curl/releases/download/curl-7_64_0-amissl/Road..." $@ + # regex $(BUILDSTEPS)/libtre.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/libtre-src.d mkdir -p $(BUILDDIR)/libtre @@ -336,8 +350,10 @@ $(SOURCEDIR)/pbl_$(VERSION_LIBPBL).tar.gz: # OpenSSL $(BUILDSTEPS)/openssl.d: $(BUILDSTEPS)/builddir.d $(BUILDSTEPS)/zlib.d $(BUILDSTEPS)/openssl-src.d +ifneq ($(TARGET),m68k-unknown-amigaos) cd $(BUILDDIR)/openssl/openssl-$(VERSION_OPENSSL) && $(env) ./Configure --prefix=$(GCCSDK_INSTALL_ENV) $(TARGET) no-shared no-threads $(EXTRAARGS_OPENSSL) cd $(BUILDDIR)/openssl/openssl-$(VERSION_OPENSSL) && $(env) make install +endif touch $@ # prepare the openssl source tree diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p deleted file mode 100644 index 5b6c913..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.c.p +++ /dev/null @@ -1,11 +0,0 @@ ---- lib/amigaos.c 2014-06-11 18:52:29.000000000 +0100 -+++ lib/amigaos.c 2014-12-20 21:34:06.686013103 +0000 -@@ -22,7 +22,7 @@ - - #include "curl_setup.h" - --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if 0 - - #include <amitcp/socketbasetags.h> - diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p deleted file mode 100644 index de22d82..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.amigaos.h.p +++ /dev/null @@ -1,11 +0,0 @@ ---- lib/amigaos.h 2014-06-11 18:52:29.000000000 +0100 -+++ lib/amigaos.h 2014-12-20 21:34:20.390013061 +0000 -@@ -23,7 +23,7 @@ - ***************************************************************************/ - #include "curl_setup.h" - --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if 0 - - bool Curl_amiga_init(); - void Curl_amiga_cleanup(); diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p deleted file mode 100644 index c9b9af3..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/lib.curl_setup.h.p +++ /dev/null @@ -1,10 +0,0 @@ ---- lib/curl_setup.h 2014-08-25 22:45:11.000000000 +0100 -+++ lib/curl_setup.h 2014-12-20 21:35:26.494012868 +0000 -@@ -311,7 +311,6 @@ - # include <exec/execbase.h> - # include <proto/exec.h> - # include <proto/dos.h> --# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) - # endif - #endif - diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p deleted file mode 100644 index 7de5cba..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_getpass.c.p +++ /dev/null @@ -1,13 +0,0 @@ ---- ./tool_getpass.c 2014-06-11 18:52:29.000000000 +0100 -+++ src/tool_getpass.c 2015-01-05 21:42:31.826011647 +0000 -@@ -24,6 +24,10 @@ - #ifndef HAVE_GETPASS_R - /* this file is only for systems without getpass_r() */ - -+#ifdef __AMIGA__ -+#undef HAVE_TERMIOS_H -+#endif -+ - #ifdef HAVE_FCNTL_H - # include <fcntl.h> - #endif diff --git a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p b/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p deleted file mode 100644 index 6237496..0000000 --- a/sdk/recipes/patches/libcurl/m68k-unknown-amigaos/src.tool_operate.c.p +++ /dev/null @@ -1,26 +0,0 @@ ---- src/tool_operate.c.orig 2019-02-14 14:10:08.086190650 +0000 -+++ src/tool_operate.c 2019-02-14 14:10:04.862196063 +0000 -@@ -33,6 +33,10 @@ - # include <fabdef.h> - #endif - -+#ifdef __AMIGA__ -+#include <proto/dos.h> -+#endif -+ - #include "strcase.h" - - #define ENABLE_CURLX_PRINTF -@@ -1856,9 +1860,9 @@ - #ifdef __AMIGA__ - if(!result && outs.s_isreg && outs.filename) { - /* Set the url (up to 80 chars) as comment for the file */ -- if(strlen(url) > 78) -- url[79] = '\0'; -- SetComment(outs.filename, url); -+ if(strlen(urlnode->url) > 78) -+ urlnode->url[79] = '\0'; -+ /*SetComment(outs.filename, urlnode->url);*/ /* cannot get a header to include that provides this function */ - } - #endif - diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p index 9833c94..5243fc5 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.c.p @@ -1,11 +1,20 @@ ---- lib/amigaos.c.old 2012-10-19 21:37:45.000000000 +0100 -+++ lib/amigaos.c 2012-10-19 21:38:09.000000000 +0100 -@@ -22,7 +22,7 @@ +--- lib/amigaos.c 2019-03-25 08:42:50.000000000 +0000 ++++ lib/amigaos.c 2019-03-30 12:49:06.680985341 +0000 +@@ -24,7 +24,7 @@ - #include "curl_setup.h" + #ifdef __AMIGA__ + # include "amigaos.h" +-# if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL) ++# if 0 + # include <amitcp/socketbasetags.h> + # endif + # ifdef __libnix__ +@@ -37,7 +37,7 @@ + #include "memdebug.h" --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if defined(__AMIGA__) && !(defined(__ixemul__) || defined(__amigaos4__)) - - #include <amitcp/socketbasetags.h> + #ifdef __AMIGA__ +-#if defined(HAVE_PROTO_BSDSOCKET_H) && !defined(USE_AMISSL) ++#if 0 + struct Library *SocketBase = NULL; + extern int errno, h_errno; diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p index 050bea7..2f62a1c 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.amigaos.h.p @@ -1,11 +1,11 @@ ---- lib/amigaos.h.old 2012-10-19 21:36:23.000000000 +0100 -+++ lib/amigaos.h 2012-10-19 21:37:26.000000000 +0100 +--- lib/amigaos.h 2019-03-25 08:42:50.000000000 +0000 ++++ lib/amigaos.h 2019-03-30 12:49:50.744493740 +0000 @@ -23,7 +23,7 @@ ***************************************************************************/ #include "curl_setup.h" --#if defined(__AMIGA__) && !defined(__ixemul__) -+#if defined(__AMIGA__) && !(defined(__ixemul__) || defined(__amigaos4__)) +-#if defined(__AMIGA__) && defined(HAVE_BSDSOCKET_H) && !defined(USE_AMISSL) ++#if 0 bool Curl_amiga_init(); void Curl_amiga_cleanup(); diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p index 7e47a50..0e52d73 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/lib.curl_setup.h.p @@ -1,23 +1,12 @@ ---- lib/curl_setup.h.old 2012-10-19 21:58:12.000000000 +0100 -+++ lib/curl_setup.h 2012-10-19 21:59:17.000000000 +0100 -@@ -323,11 +323,15 @@ - - #ifdef __AMIGA__ - # ifndef __ixemul__ --# include <exec/types.h> --# include <exec/execbase.h> --# include <proto/exec.h> --# include <proto/dos.h> --# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) -+# ifdef __amigaos4__ -+# include <unistd.h> -+# else -+# include <exec/types.h> -+# include <exec/execbase.h> -+# include <proto/exec.h> -+# include <proto/dos.h> -+# define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) -+# endif +--- lib/curl_setup.h 2019-03-30 13:44:08.576270700 +0000 ++++ lib/curl_setup.h 2019-03-30 13:44:33.011975643 +0000 +@@ -314,7 +314,8 @@ + # include <exec/execbase.h> + # include <proto/exec.h> + # include <proto/dos.h> +-# ifdef HAVE_PROTO_BSDSOCKET_H ++# define HAVE_SELECT 1 ++# if 0 + # include <proto/bsdsocket.h> /* ensure bsdsocket.library use */ + # define select(a,b,c,d,e) WaitSelect(a,b,c,d,e,0) # endif - #endif - diff --git a/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p b/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p index 6237496..4c9a726 100644 --- a/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p +++ b/sdk/recipes/patches/libcurl/ppc-amigaos/src.tool_operate.c.p @@ -1,26 +1,11 @@ ---- src/tool_operate.c.orig 2019-02-14 14:10:08.086190650 +0000 -+++ src/tool_operate.c 2019-02-14 14:10:04.862196063 +0000 -@@ -33,6 +33,10 @@ - # include <fabdef.h> - #endif - -+#ifdef __AMIGA__ -+#include <proto/dos.h> -+#endif -+ - #include "strcase.h" - - #define ENABLE_CURLX_PRINTF -@@ -1856,9 +1860,9 @@ - #ifdef __AMIGA__ - if(!result && outs.s_isreg && outs.filename) { +--- src/tool_operate.c 2019-03-30 12:33:41.315465662 +0000 ++++ src/tool_operate.c 2019-03-30 12:42:36.643382219 +0000 +@@ -1872,7 +1872,7 @@ static CURLcode operate_do(struct Global /* Set the url (up to 80 chars) as comment for the file */ -- if(strlen(url) > 78) -- url[79] = '\0'; -- SetComment(outs.filename, url); -+ if(strlen(urlnode->url) > 78) -+ urlnode->url[79] = '\0'; -+ /*SetComment(outs.filename, urlnode->url);*/ /* cannot get a header to include that provides this function */ + if(strlen(urlnode->url) > 78) + urlnode->url[79] = '\0'; +- SetComment(outs.filename, urlnode->url); ++ IDOS->SetComment(outs.filename, urlnode->url); } #endif -- Cross-compilation toolchains and environments

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