Hi All, I am trying to build the lowrisc 0.5 release for a custom Virtex 7 2000T device. To begin with I tried to build the nexus 4 ddr design, but the implementation fails. Has anyone been successfull in pulling the latest 0.5 release from github and building it. I have attached the vivado log in this mail. Looking forward for any help.

Hi Alex, Thank you for getting back. I am sorry, it was my mistake. The vivado tool ran out of memory and crashed. I was able to build it successfully on a bigger server. I have started with the port to V2000T, looking through the scripts to figure out the block design and the additional clocks required. Thanks & Regards, Anup Kini. On Tue, Jan 23, 2018 at 2:03 PM, Alex Bradbury <asb(a)lowrisc.org&gt; wrote: > On 19 January 2018 at 10:27, Anup Kini <anupkini(a)gmail.com&gt; wrote: >> Hi All, >> >> I am trying to build the lowrisc 0.5 release for a custom Virtex 7 2000T >> device. >> >> To begin with I tried to build the nexus 4 ddr design, but the >> implementation fails. >> Has anyone been successfull in pulling the latest 0.5 release from github >> and building it. >> >> I have attached the vivado log in this mail. >> Looking forward for any help. > Hi Anup. Thanks for trying our latest release. The log doesn't seem to > have made it through with your message - could you perhaps try to > share it again? > > Thanks, > > Alex >

Hi Jonathan, Thanks for pointing out the ethernet IP. Currently, I need to boot linux on a RISC-V based system and found lowrisc to be simple and easy to follow. I can do without the ethernet IP for now, login through the UART interface and work on building a open-emdedded layer for the filesystem. I did look at the v0.2, untethered version also, the main point being easy to port to the Virtex 2000T boards that I have here. The end goal would be to integrate with REDEFINE, a massively parallel many core architecture (this work was presented at the RISC V Workshop 2016. Video @ 7:40 mins <https://www.youtube.com/watch?v=PCzAOYJa-xY>)

On 23 January 2018 at 09:17, Anup Kini <anupkini(a)gmail.com&gt; wrote: > Hi Jonathan, > > Thanks for pointing out the ethernet IP. > > Currently, I need to boot linux on a RISC-V based system and found lowrisc > to be simple and easy to follow. > I can do without the ethernet IP for now, login through the UART interface > and work on building a open-emdedded layer for the filesystem. > I did look at the v0.2, untethered version also, the main point being easy > to port to the Virtex 2000T boards that I have here. > > The end goal would be to integrate with REDEFINE, a massively parallel many > core architecture (this work was presented at the RISC V Workshop 2016. Video > @ 7:40 mins <https://www.youtube.com/watch?v=PCzAOYJa-xY>) Interesting, are there any published papers on REDEFINE? Best, Alex

The clocks (on NexysDDR) are: 100MHz - incoming crystal oscillator 200MHz - mig_sys_clk to DDR controller (divided down to 25MHz for processor clk output) 60MHz - clk_io_uart to UART (divided down to 12MHz for trace debugger interface) 120MHz - clk_pixel to VGA monitor 50MHz (clk_rmii, clk_rmii_quad quadrature clocks) to Ethernet RMII The mig_ui_clk is 50MHz corresponding to the 2:1 clock converter for AXI DDR memory. On a different board you may well be able to go faster but these are the settings that we know work on the Artix-7. Regards, Jonathan On 29/01/18 09:21, Anup Kini wrote: Hi All, I have gone through the code and need some clarification regarding the clocks so that I can configure the mig correctly. - riscv processor clock - 50 MHz - from mig additonal clock - Is this correct ? - mig - ui_clk - this returns 200 MHz, is this correct ? - uart16550 - is this clocked at 200 MHz or 50 MHz Looking forward for some help. Thanks & Regards, Anup Kini. On Tue, Jan 23, 2018 at 2:51 PM, Alex Bradbury <asb(a)lowrisc.org&gt; wrote: > On 23 January 2018 at 09:17, Anup Kini <anupkini(a)gmail.com&gt; wrote: > > Hi Jonathan, > > > > Thanks for pointing out the ethernet IP. > > > > Currently, I need to boot linux on a RISC-V based system and found > lowrisc > > to be simple and easy to follow. > > I can do without the ethernet IP for now, login through the UART > interface > > and work on building a open-emdedded layer for the filesystem. > > I did look at the v0.2, untethered version also, the main point being > easy > > to port to the Virtex 2000T boards that I have here. > > > > The end goal would be to integrate with REDEFINE, a massively parallel > many > > core architecture (this work was presented at the RISC V Workshop 2016. > Video > > @ 7:40 mins <https://www.youtube.com/watch?v=PCzAOYJa-xY>) > > Interesting, are there any published papers on REDEFINE? > > Best, > > Alex >