5:18 p.m.
Hello everyone,
The GSOC deadline is over and I would not be able to submit a propsal,
however I would still like to contribute this independent of GSOC as I see
a strong opportunity to learn something valuable.
I went through the entire source code, but I was unable to find any
reference to Xilinx blocks in the source code. Is it generated from the
Chisel source code? Please provide pointers
Yours sincerely,
Nishant
5:58 p.m.
On 25 March 2016 at 16:18, Nishant Pani <np661944(a)gmail.com> wrote:
Hello everyone,
The GSOC deadline is over and I would not be able to submit a propsal,
however I would still like to contribute this independent of GSOC as I see
a strong opportunity to learn something valuable.
Hi Nishant. First of all, we'd warmly welcome contributions from you -
I'll let Wei say more about the current source code organisation. I
will just point out that there are actually 2 hours left to submit a
proposal for GSoC.
Best,
Alex
5:11 p.m.
Alex and Stefan,
Thanks a lot. Can you tell me what is the purpose of socip folder in the
source code? It doesn't make sense to me why you would include that UART
folder when you are already using Xilinx's IP for the UART controller
Sincerely,
Nishant
7:34 p.m.
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On 26.03.2016 17:11, Nishant Pani wrote:
Alex and Stefan,
Thanks a lot. Can you tell me what is the purpose of socip folder
in the source code? It doesn't make sense to me why you would
include that UART folder when you are already using Xilinx's IP for
the UART controller
Sincerely, Nishant
It is essentially a git submodule, meaning it is another git
repository linked in. I think the UART was used in some other branch
or so.
Best,
Stefan
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7:16 p.m.
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On 25.03.2016 17:18, Nishant Pani wrote:
Hello everyone,
The GSOC deadline is over and I would not be able to submit a
propsal, however I would still like to contribute this independent
of GSOC as I see a strong opportunity to learn something valuable.
I went through the entire source code, but I was unable to find
any reference to Xilinx blocks in the source code. Is it generated
from the Chisel source code? Please provide pointers
Yours sincerely, Nishant
Hi Nishant,
the Xilinx blocks are generated automatically:
https://github.com/lowRISC/lowrisc-nexys4/blob/b2459b9fafe9336c513c5e7e6
29c87de7595fc45/script/make_project.tcl#L68
Best,
Stefan
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2815
days inactive
2816
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4 comments
3 participants
participants (3)
-
Alex Bradbury -
Nishant Pani -
Stefan Wallentowitz