8:17 a.m.
Hello,
I want to configure LowRISC to have two tiles, I am using V0.3. So I disabled the FPU to
save area, and modify the tool chain accordingly. Then I increased NTILES to 2. I am able
to download the design into the FPGA, but when I use "opensocdebugd", the
program stuck after printing the following lines:
Open SoC Debug Daemon
Backend: uart
Did I miss something?
Best regards,
Armia
5 p.m.
This is a major change you have made. You should start by getting the ISA tests running
again in multi core, and once that is successful, proceed to FPGA simulation and finally
FPGA bitstream. You will need to adapt the software to detect multi-cores properly I
expect. I don’t know if the trace debugger was designed for multi-core, you can disable it
for your first attempt.
Sent from my iPhone
On 5 Dec 2017, at 23:17, Armia Salib <armiasalib(a)yahoo.com>
wrote:
Hello,
I want to configure LowRISC to have two tiles, I am using V0.3. So I disabled the FPU to
save area, and modify the tool chain accordingly. Then I increased NTILES to 2. I am able
to download the design into the FPGA, but when I use "opensocdebugd", the
program stuck after printing the following lines:
Open SoC Debug Daemon
Backend: uart
Did I miss something?
Best regards,
Armia
5:16 p.m.
On 12/06/2017 09:00 AM, Dr Jonathan Kimmitt wrote:
I don’t know if the trace debugger was designed for multi-core, you
can disable it for your first attempt.
just to answer that part of the question: trace debugging works with
multiple cores, every core is seen as independent unit to collect traces
from. That being said, I don't think it has ever been used this way on
lowrisc. (We use it on OpTiMSoC with multiple cores, however.)
Philipp
2123
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participants (3)
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Armia Salib -
Dr Jonathan Kimmitt -
Philipp Wagner