On 31 December 2016 at 10:25, Stefan Wallentowitz
<stefan at wallentowitz.de
* On 30.12.2016 20:42, Brad Walker wrote:
noticed there is a port, with bitstreams, of the Low-Risc processor to
*>>* the Nexy Artix-7 FPGA board.
*>>>>* Has anyone done any work to get the processor instantiated on the
*>>* Zynq family (i.e. Zedboard/Microzed) of FPGAs?
*>>* Hi Brad,
*>>* the first release of lowRISC was actually moving away from the Zynq
*>* platform, because the original Rocket chip was (is?) tethered to the ARM
*>* on that. For that we moved to a logic only FPGA. I think moving back to
*>* the Zynq and use the AXI (for example with Xilibus or so) to communicate
*>* with the debug interface instead of the Rocket's HTIF is a neat project.
* If you or anyone else want to undertake it, I would be happy to assist.*
I would tend to agree that using the Zynq based FPGA boards (i.e. Zedboard,
etc.) have programmable logic that might be a little bit on the low side.
So my thinking was something a little bit more beefy like the ECP5 from
Lattice or maybe even doing a custom FPGA board using a beefier FPGA from
Does anyone have a utilization report from Vivado so that I see what the
"final" bitstream usage looks like?