Hi folks, hi Alex, well for one, I am still refining a document about an integrated debug/virtualisation/device SoC design. Regretfully I dont have much time to work on it so it keeps being a work-in-progress. If there I repost it here again but its 5th revision isn't 100% complete yet. Now if I only had the time to create it in Chissel (and time to learn Chissel enough ;-)). Alex, do you we could find some time to discuss the current proposal? Preferably together with Rob? On or off-list?