I haven’t studied that module but I am going to go out on a limb here to try and give you
an insight, and I can state the general principle that the hardware description is a
shallow embedding within the Scala/Chisel framework and so, unlike system verilog, you
will not find lines of Scala which directly represent the corresponding floating point
operations. What you will find is a higher order framework of functions and objects which,
when compiled and executed, causes the FPU unit to be generated, and subsequently dumped
as Verilog code. Hence, you will find a formal separation between abstract blocks of
declarative code (stating what should be done) and imperative code (stating, step by step,
how something should be done). So we end up with a system which is powerful but hard to
understand, at least for outsiders. So without simplifying too much, I’m guessing that the
hardfloat code base contains the what code and FPU.scala contains the how code which
instantiates the FPU within the Rocket processor. Of course there is nothing within the
Chisel framework or the Scala language that enforces a clean separation between different
programming styles or intents. I’m sure when you’ve studied the code for a while you will
realise the shortcomings of my hand waving explanation.
Sent from my iPhone
On 21 Nov 2017, at 00:04, Aleksandar Pajkanovic
<aleksandar.pajkanovic(a)etf.unibl.org> wrote:
Hello, thank you, dr Kimmitt, thank you very much for taking the time to look into my
quesetion.
For some reason, your reply did not end up in my inbox, so I have no possibility on
choosing Reply-to-All, so I hope this way the message will end up on the corresponding
thread.
Thank you for elaborating on the possibilities to characterize the performance of the
FPU. To conclude, basically, we need to generate the whole thing, be it LowRISC chip or
anything else, and only from there we could make a claim about FPU's performance (in
the context of speed, area and power consumption).
I hope you won't mind me now completely moving to the second part of my initial
query. Can you tell me about the relation between the hardfloat submodule and the
FPU.scala file?
If all of the FPU is generated based on the HDL code of the hardfloat submodule, what
does FPU.scala actually do?
Thanks a lot,
Aleksandar