11:59 p.m.
Dear all,
Recently I have encountered some problems regarding FPGA DEMO generate
bitstream.
ideally,
after generating bitstream
cd $TOP/fpga/board/$FPGA_BOARD
make bitstream
The final bit stream is located at
lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit.
However, in my case, there is no such folder called impl_1
*~/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.runs$
lsaxi_bram_ctrl_0_synth_1 axi_quad_spi_0_synth_1
mig_7series_0_synth_1axi_clock_converter_0_synth_1
axi_uart16550_0_synth_1 synth_1*
and my error message after make bitstream
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
*# wait_on_run synth_1[Mon Sep 26 17:39:13 2016] Waiting for synth_1
to finish...[Mon Sep 26 17:39:47 2016] synth_1 finishedwait_on_run:
Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak =
1052.801 ; gain = 12.504 ; free physical = 995 ; free virtual = 13110#
launch_runs impl_1 -to_step write_bitstreamERROR: [Common 17-70]
Application Exception: Failed to launch run 'impl_1' due to failures
in the following
run(s):axi_uart16550_0_synth_1axi_bram_ctrl_0_synth_1mig_7series_0_synth_1axi_clock_converter_0_synth_1These
failed run(s) need to be reset prior to launching 'impl_1' again.INFO:
[Common 17-206] Exiting Vivado at Mon Sep 26 17:39:47
2016...Makefile:110: recipe for target
'lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit'
failedmake: ***
[lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit] Error 1*
There is also warning messages regarding could not locate several files
*WARNING: [IP_Flow 19-3664] IP 'axi_quad_spi_0' generated file not
found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0_stub.v'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'axi_clock_converter_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0_sim_netlist.vhdl'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'mig_7series_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/mig_7series_0/mig_7series_0_sim_netlist.v'.
Please regenerate to continue.*
Please advise. I tried make cleanall and make bitstream several times.
Thank you for your help
Weizhong Huang
8:12 a.m.
On 26.09.2016 23:59, weizhong huang wrote:
Please advise. I tried make cleanall and make bitstream several
times.
Thank you for your help
Weizhong Huang
Hi,
which version of Vivado are you using?
Can you try changing fpga/board/nexys4_ddr/script/make_project.tcl:
diff --git a/script/make_project.tcl b/script/make_project.tcl
index 9b87dc6..9c97e96 100644
--- a/script/make_project.tcl
+++ b/script/make_project.tcl
@@ -207,6 +207,7 @@ set files [list [file normalize
"$origin_dir/constraint/pin_plan.xdc"] \
set file_added [add_files -norecurse -fileset $obj $files]
# generate all IP source code
+upgrade_ip [get_ips]
generate_target all [get_ips]
# force create the synth_1 path (need to make soft link in Makefile)
Cheers,
Stefan
1:12 p.m.
Hello Weizhong,
If I remember it right, you have reported nearly the same error days ago.
Have you ever been able to generate bitstream even once in this
directory or it never succeeded?
For the error message, the problem remains the same.
Somehow Vivado fails to synthesize the IPs needed for the lowRISC fpag
project.
When you do make cleanall, have you double checked that the
lowrisc-chip-imp directory is indeed deleted?
Please close all vivado process (double check with "ps -ef | grep vivdo").
If any vivado process is using the lowrisc-chip-imp directory, make
cleanall will fail to delete it.
Also, you may try
make cleanall
make vivado
This will create a vivado project and give you the Vivado GUI.
You can press the synthesis button in GUI. It might give you better
information about what goes wrong.
Also I notice that you are running in fpga/board/kc705.
Right now we have not updated the kc705 support for a long time.
If your target is the latest debug-v0.3 release, you need to revise the
kc705 project according to the nexys4_ddr manually.
Simply make bitstream in that directory will not work.
-Wei
On 26/09/16 22:59, weizhong huang wrote:
Dear all,
Recently I have encountered some problems regarding FPGA DEMO generate
bitstream.
ideally,
after generating bitstream
cd $TOP/fpga/board/$FPGA_BOARD
make bitstream
The final bit stream is located at
lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit.
However, in my case, there is no such folder called impl_1
*~/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.runs$
lsaxi_bram_ctrl_0_synth_1 axi_quad_spi_0_synth_1
mig_7series_0_synth_1axi_clock_converter_0_synth_1
axi_uart16550_0_synth_1 synth_1*
and my error message after make bitstream
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
*# wait_on_run synth_1[Mon Sep 26 17:39:13 2016] Waiting for synth_1
to finish...[Mon Sep 26 17:39:47 2016] synth_1 finishedwait_on_run:
Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak =
1052.801 ; gain = 12.504 ; free physical = 995 ; free virtual = 13110#
launch_runs impl_1 -to_step write_bitstreamERROR: [Common 17-70]
Application Exception: Failed to launch run 'impl_1' due to failures
in the following
run(s):axi_uart16550_0_synth_1axi_bram_ctrl_0_synth_1mig_7series_0_synth_1axi_clock_converter_0_synth_1These
failed run(s) need to be reset prior to launching 'impl_1' again.INFO:
[Common 17-206] Exiting Vivado at Mon Sep 26 17:39:47
2016...Makefile:110: recipe for target
'lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit'
failedmake: ***
[lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit] Error 1*
There is also warning messages regarding could not locate several files
*WARNING: [IP_Flow 19-3664] IP 'axi_quad_spi_0' generated file not
found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_quad_spi_0/axi_quad_spi_0_stub.v'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'axi_clock_converter_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0_sim_netlist.vhdl'.
Please regenerate to continue.WARNING: [IP_Flow 19-3664] IP
'mig_7series_0' generated file not found
'/home/hplp/lowRISC/DIR/lowrisc-chip/fpga/board/kc705/lowrisc-chip-imp/lowrisc-chip-imp.srcs/sources_1/ip/mig_7series_0/mig_7series_0_sim_netlist.v'.
Please regenerate to continue.*
Please advise. I tried make cleanall and make bitstream several times.
Thank you for your help
Weizhong Huang
2628
days inactive
2629
days old
2 comments
3 participants
participants (3)
-
Stefan Wallentowitz -
Wei Song -
weizhong huang