Thanks Wei,
In my application I need to prepare some data in DRAM to be read by a DMA.
So how can I be sure that all data go to DRAM without remain trapped in the
caches if there is no flush instruction and I cannot remap the DRAM/IO
within Linux?
Francesco
On Thu, Aug 18, 2016 at 10:22 AM Wei Song <ws327(a)cam.ac.uk> wrote:
Hello Francesco,
All PCRs registers are mapped to CSRs using the same address.
The addresses of CSRs denote the R/W permission and privilege level.
For timer, I suppose user mode program can read CSR.time, which will
read the PCR.ptime.
For the memory and IO maps, they are machine mode CSRs/PCRs.
I do not think Linux or bbl should change them because such operation is
very dangerous with unknown consequences.
For example, if the memory map is changed, the data in L1/2$ become
stale and potentially very harmful considering stale data being written
back to memory!
This is the major reason that both maps have been removed in later
releases.
Best regards,
Wei
On 18/08/2016 15:11, Francesco Viggiano wrote:
> Hi guys,
>
> I'm using the untethered version 0.2 of the lowrisc-chip.
> I'm wondering, how can I access (write and read) PCR register within a
> Linux application? (for example to remap the address space or read the
> timer. In bare metal you use a syscall (in syscall.c) to have access to
> those register in a ''machine mode'' (in crt.S). I don't see
anything
> similar in the bbl code.
>
> Thanks for your help,
>
> Francesco
--
| Francesco Viggiano, Columbia University, Staff associate researcher at
Computer Science Building |
| Phone: +1 646-9829-535, Skype ID: francesco.vgg |
| Department of Computer Science 1214 Amsterdam Avenue |
| Columbia University Mail Code 0401 | New York, NY 10027-7003 |